Technical data

PMCspan PMC Carrier Module Installation and Use (6806800A59B)
3 Functional Description
16
PMC Performance
All PMCspan models support 32-bit PCI operations at 33 MHz on the PMC (secondary) side.
The PMCspan16E-002 primary carrier module supports 32-bit PCI operations on the processor
(primary) side. Refer to the PCI6150 data book, listed in Appendix A, Related Documentation
for PCI transaction timing information across the bridge.
Writes to the PCI bus are also posted by the Raven chip ASIC, so this section will focus mainly
on read cycles. The read access latency for PMCspan-bound cycles initiated by 60X bus master
consists of the following components:
T
start
Start-up time (TS# to PCI bus Request).
T
start
is 6 system clocks.
T
arb
On-board PCI bus arbitration time.
T
ac
On-board PCI access time (FRAME# to TRDY#).
T
lat
Latency through PCI-to-PCI bridge.
T
delay
Delay time from TRDY# on PCI to TA# on 60X bus. T
delay
is 4 system clocks.
Table 3-1 shows the access timings for various types of transfers initiated by a 60X system bus
master to a PMCspan module.
Table 3-1. PowerPC 60x Bus to PMCspan PMC Access Timing
Access Type
System Clock Periods Required for:
Total
Clock
s
1st Beat
2nd
Beat
3rd Beat 4th Beat
4-Beat Read (32-bit PCI
Target)
49 1 1 1 52
4-Beat Write (32-bit PCI Target)
41117
1-Beat Read (aligned, 4 bytes
or less)
38 - - - 38
1-Beat Write
4---4
Notes
Write cycles are posted by the Raven ASIC.
Assumes no pipeline. Pipelined cycles would improve these
numbers.
T
arb
is assumed to be 4 system clocks (2 PCI clocks).
T
ac
is assumed to be 6 system clocks (3 PCI clocks): Medium
DEVSEL# target, zero wait PCI timing.