Technical data

3
PMCspan PMC Carrier Module Installation and Use (6806800A59B)
13
3 Functional Description
Introduction
This chapter describes the physical and electrical structure of the PMCspan. Figure 3-1 and
Figure 3-2 show the detailed block diagrams of the PMCspan and its primary interfaces.
PMC module I/O is available through the PMCspan front panel opening (for PMC modules with
front panel connectors) or through the PMCspan VMEbus P2 backplane connector.
PCI-to-PCI Bridge Chip
The primary component on the PMCspan is the PCI6150 PCI-to-PCI bridge chip. This device
provides the interface between the primary PCI bus (processor side), and the secondary PCI
bus, which provides the interface to the PMC module. The bridge chip connects to the VMEbus
processor module PCI bus through the PCI Expansion connector. The secondary PCI bus
connects to each of the PCM slots and a an optional secondary expansion connector. For a
detailed description of the PCI6150 chip, refer to the data book listed in Appendix A, Related
Documentation.
The PCI6150 PCI-to-PCI Bridge chip supports a 32-bit primary bus interface and a 32-bit
secondary bus interface. This chip provides full support for delayed transactions which enables
the buffering of memory read, I/O, and configuration transactions. It supports buffering of
simultaneous multiple posted write and delayed transactions in both directions.
The PCI6150 has clock and arbitration pins to support PCI bus masters on the secondary bus.
These are used to provide clocks an bus arbitration for the PMC module. The PCI6150 supports
concurrent operation on the primary and secondary PCI busses providing traffic isolation
between the primary and secondary busses.