Technical data

7 Programming the MVME5100
MVME51005E Single Board Computer Installation and Use (6806800A38B)
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Table 7-5. Devices Affected by Various Resets
Endian Issues
The MVME5100 supports both little-endian (e.g., Windows NT) and big-endian (e.g., AIX)
software. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI
bus is inherently little-endian. The following sections summarize how the MVME5100 handles
software and hardware differences in big- and little-endian operations. For further details on
endian considerations, refer to the MVME5100-Series Single Board Computer Programmer’s
Reference Guide.
Processor/Memory Domain
The MPC750 processor can operate in both big-endian and little-endian mode. However, it
always treats the external processor/memory bus as big-endian by performing address
rearrangement and reordering when running in little-endian mode. The MPC registers in the
Hawk MPU/PCI bus bridge controller, SMC memory controller, as well as DRAM, Flash and
system registers, always appear as big-endian.
Role of the Hawk ASIC
Because the PCI bus is little-endian, the PHB portion of the Hawk performs byte swapping in
both directions (from PCI to memory and from the processor to PCI) to maintain address
invariance while programmed to operate in big-endian mode with the processor and the
memory subsystem.
In little-endian mode, the PHB reverse-rearranges the address for PCI-bound accesses and
rearranges the address for memory-bound accesses (from PCI). In this case, no byte swapping
is done.
Device Affected Proces
sor
Hawk
ASIC
PCI
Devices
ISA
Devices
VMEbus
(as system
controller)
Reset Source
Power-On reset √√√ √ √
Reset switch √√√ √ √
Watchdog reset √√√ √ √
VME
SYSRESET∗signal
√√√ √ √
VME System SW
reset
√√√ √ √
VME Local SW reset √√√ √
VME CSR reset √√√ √
Hot reset (Port 92) √√√ √
PCI/ISA reset √√