Technical data

7 Programming the MVME5100

MVME51005E Single Board Computer Installation and Use (6806800A38B)

Interrupt Handling

The Hawk ASIC, which controls the PHB (PCI Host Bridge) and the MPU/local bus interface

functions on the MVME5100, performs interrupt handling as well. Sources of interrupts may be

any of the following:

❏ The Hawk ASIC itself (timer interrupts, transfer error interrupts or memory error

interrupts)

❏ The processor (processor self-interrupts)

❏ The PCI bus (interrupts from PCI devices)

❏ The ISA bus (interrupts from ISA devices)

Figure 7-2 illustrates interrupt architecture on the MVME5100. For details on interrupt handling,

refer to the MVME5100-Series Single Board Computer Programmer’s Reference Guide.

Figure 7-2. MVME5100 Interrupt Architecture

11559.00 9609

PIB

(8529 Pair)

Processor

INT_

MCP_

Hawk MPIC

INT

SERR_& PERR_

PCI Interrupts

ISA Interrupts