i MVME51005E Single Board Computer Installation and Use 6806800A38B August 2008 Edition
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Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Emerson is aware.
Flammability All Emerson PWBs (printed wiring boards) are manufactured with a flammability rating of 94V0 by UL-recognized manufacturers. EMI Caution ! Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection. Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry.
CE Notice (European Community) Warning ! This is a Class A product. In a domestic environment, this product may cause radio interference, in which case the user may be required to take adequate measures. Warning Emerson products with the CE marking comply with the EMC Directive (89/336/EEC).
Contents About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Overview of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi Conventions Used in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xvii Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 3 PPCBug Firmware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPCBug Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implementation and Memory Requirements . . . . . . . . . . . . .
Contents RAM500 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom Side Memory Expansion Connector (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Side Memory Expansion Connector (J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM500 Programming Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents EMC Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 B Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Solving Startup Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 C Thermal Analysis . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 2-1. Figure 4-1. Figure 5-1. Figure 5-2. Figure 7-1. Figure 7-2. Figure C-1. Figure C-2. Figure C-3. Figure C-4. MVME5100 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MVME5100 Installation and Removal From a VMEbus Chassis . . . . . . . . . . . . . . . . . . . 7 Typical PMC Module Placement on an MVME5100 . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 1-1. Table 3-1. Table 3-2. Table 4-1. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 6-6. Table 6-7. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table A-1. Table A-2. Table B-1. Table C-1. Table C-2. Table D-1. Table D-2. Table D-3. Manually Configured Headers/Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . .
About This Manual The MVME51005E Single Board Computer Installation and Use provides the information you will need to install and configure your MVME51005E Single Board Computer. It provides specific preparation and installation information and data applicable to the board. The MVME51005E will hereafter be referred to as the MVME5100.
About This Manual Model Number Description Related Products PMCSPAN26E-002 Primary PMCSPAN with original VME Scanbe ejector handles. PMCSPAN26E-010 Secondary PMCSAN with original VME Scanbe ejector handles. RAM5005E-006 Stackable (top) 256MB ECC SDRAM mezzanine. RAM5005E-016 Stackable (bottom) 256MB ECC SDRAM mezzanine. RAM5005E-010 Stackable (top) 512MB ECC SDRAM mezzanine. RAM5005E-020 Stackable (bottom) 512MB ECC SDRAM mezzanine.
About This Manual Chapter 7, Programming the MVME5100, provides a description of the memory maps on the MVME5100 including tables of default processor memory maps, suggested CHRP memory maps and Hawk PPC register values for suggested memory maps. The remainder of the chapter provides some programming considerations. Appendix A, Specifications, provides the standard specifications for the MVME5100, as well as some general information on cooling.
About This Manual CTRL represents the Control key. Execute control characters by pressing the Ctrl key and the letter simultaneously, for example, Ctrl-d.
1 Hardware Preparation and Installation 1 Introduction This chapter provides information on hardware preparation and installation for the MVME5100 Series of Single Board Computers. Note Unless otherwise specified, the designation “MVME5100” refers to all models of the MVME5100-series Single Board Computers. Getting Started The following subsections include information helpful in preparing your equipment.
1 Hardware Preparation and Installation ❏ Operating system (and/or application software) Unpacking Instructions Avoid touching areas of integrated circuitry; static discharge can damage these circuits. Caution Note If the shipping carton(s) is/are damaged upon receipt, request that the carrier's agent be present during the unpacking and inspection of the equipment.
1 Hardware Preparation and Installation Preparation This section includes subsections on hardware configuration that may need to be performed immediately before and after board installation. It includes a brief reminder on setting bits in control registers, setting jumpers for the appropriate configuration, and other VME data considerations.
1 Hardware Preparation and Installation Table 1-1.
1 Hardware Preparation and Installation PMC I/O Mode 2 4 6 SBC I/O Mode J10 2 4 1 3 6 J10 1 3 5 2 4 6 J17 5 2 4 6 1 3 5 J17 1 3 5 J4 J4 123456 7 8 123456 7 8 For rear panel LAN, jumper entire 8 pin header on J4 PMC/SBC (761/IPMC) Mode Selection There are five headers associated with the selection of the PMC or SBC mode: J4, J6 J10, J17 and J20.
1 Hardware Preparation and Installation Multiple MVME5100 boards may be installed in a single VME chassis; however, each must have a unique VMEbus address. Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the operational status of the processor(s). Installation This section discusses the installation of PMCs onto the MVME5100, installation of PMCspan modules onto the MVME5100, and the installation of the MVME5100 into a VME chassis.
1 Hardware Preparation and Installation PMC Modules PMC modules mount on top of the MVME5100. Perform the following steps to install a PMC module on your MVME5100. Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing and adjusting. Warning Caution Note Inserting or removing modules with power applied may result in damage to module components. Avoid touching areas of integrated circuitry, static discharge can damage these circuits.
1 Hardware Preparation and Installation Figure 1-3. Typical PMC Module Placement on an MVME5100 Primary PMCspan To install a PMCspan16E-002 PCI expansion module on your MVME5100, perform the following steps while referring to the figure on the next page: Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Warning Caution Note Inserting or removing modules with power applied may result in damage to module components.
1 Hardware Preparation and Installation – Insert the threaded end into the standoff hole at each corner of the MVME5100. – Thread the locking nuts into the standoff tips and tighten. 5. Place the PMCspan on top of the MVME5100. Align the mounting holes in each corner to the standoffs and align PMCspan connector P4 with MVME5100 connector J25. PMCspan MVME5100 2081 9708 Figure 1-4. PMCspan-002 Installation on an MVME5100 6.
1 Hardware Preparation and Installation Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Warning Caution Note Inserting or removing modules with power applied may result in damage to module components. Avoid touching areas of integrated circuitry, static discharge can damage these circuits.
1 Hardware Preparation and Installation 4. Remove four screws (Phillips type) from the standoffs in each corner of the primary PCI expansion module. 5. Attach the four standoffs from the PMCspan-010 mounting kit to the PMCspan-002 by screwing the threaded male portion of the standoffs in the locations where the screws were removed in the previous step. 6. Place the PMCspan-010 on top of the PMCspan-002.
1 Hardware Preparation and Installation – If you do not intend to use the MVME5100 as system controller, it can occupy any unused card slot. 4. Slide the MVME5100 (and PMCspans if used) into the selected card slot(s). Verify that the module or module(s) seated properly in the P1 and P2 connectors on the chassis backplane. Do not damage or bend connector pins. 5.
2 Operation 2 Introduction This chapter provides operating instructions for the MVME5100 Single Board Computer. It includes necessary information about powering up the system along with the functionality of the switches, status indicators and I/O ports on the front panels of the board.
2 Operation Note SYSRESET# remains asserted for at least 200 ms, as required by the VMEbus specification. Status Indicators There are two Light-Emitting Diode (LED) status indicators located on the MVME5100 front panel. They are labeled BFL and CPU. RST Indicator (DS1) The yellow BFL LED indicates board failure; this indicator is also illuminated during reset as an LED test. The BFL is set if the MODFAIL Register or FUSE Register is set.
2 Operation System Powerup After you have verified that all necessary hardware preparation is done, that all connections were made correctly and that the installation is complete, you can power up the system. Initialization Process The MPU, hardware and firmware initialization process is performed by the PPCBug firmware upon system powerup or system reset. The firmware initializes the devices on the MVME5100 in preparation for booting an operating system.
3 PPCBug Firmware 3 Introduction The PPCBug firmware is the layer of software just above the hardware. The firmware provides the proper initialization for the devices on the MVME5100 upon powerup or reset. This chapter describes the basics of the PPCBug and its architecture. It also describes the monitor (interactive command portion of the firmware), and provides information on using the PPCBug debugger and the special commands. A complete list of PPCBug commands is also provided.
3 PPCBug Firmware ❏ If you are in the debugger directory, the debugger prompt PPC6-Bug> is displayed and you have all of the debugger commands at your disposal. ❏ If you are in the diagnostic directory, the diagnostic prompt PPC6-Diag> is displayed and you have all of the diagnostic commands at your disposal as well as all of the debugger commands. Because PPCBug is command-driven, it performs its various operations in response to user commands entered at the keyboard.
3 PPCBug Firmware For example, if a breakpoint has been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program. Alternately, the user program could return to the debugger by means of the System Call Handler routine RETURN (described in the PPCBug Firmware Package User’s Manual). For more about this, refer to the GD, GO and GT command descriptions in the PPCBug Firmware Package User’s Manual, listed in Appendix D, Related Documentation .
3 PPCBug Firmware 19. Enables the superscalar feature of the MPU (superscalar processor boards only). 20. Verifies the external bus clock speed of the MPU. 21. Determines the debugger's console/host ports and initializes the PC16550A. 22. Displays the debugger's copyright message. 23. Displays any hardware initialization errors that may have occurred. 24. Checksums the debugger object and displays a warning message if the checksum failed to verify. 25. Displays the amount of local read/write memory found.
3 PPCBug Firmware Ethernet Address = 0001AF2A0A57 Primary SCSI Identifier = 07 System Serial Number = nnnnnnnn System Identifier = Emerson MVME5100 License Identifier = nnnnnnnn The Board Information Block parameters shown above are left-justified character (ASCII) strings padded with space characters. The Board Information Block is factory-configured before shipment. There is no need to modify block parameters unless the NVRAM is corrupted.
3 PPCBug Firmware If a value of zero is specified, memory will continue to be increased as needed until half of the available memory is consumed (that is, 32MB in a 64MB system). This mode is useful for determining the full memory required for a specific configuration. Once this is determined, a hard value may be given to the parameter and it is guaranteed that no memory will be used over this amount. The default value for this parameter is one.
3 PPCBug Firmware Network PReP-Boot Mode Enable [Y/N] = N? Y Enable PReP-style network booting (same boot image from a network interface as from a mass storage device). N Do not enable PReP-style network booting. (Default) Negate VMEbus SYSFAIL* Always [Y/N] = N? Y Negate the VMEbus SYSFAIL∗ signal during board initialization. N Negate the VMEbus SYSFAIL∗ signal after successful completion or entrance into the bug command monitor.
3 PPCBug Firmware NVRAM Bootlist (GEV.fw-boot-path) Boot at power-up only [Y/N] = N? Y Give boot priority to devices defined in the fwboot-path GEV at powerup reset only. N Give powerup boot priority to devices listed in the fw-boot-path GEV at any reset. (Default) NVRAM Bootlist (GEV.fw-boot-path) Boot Abort Delay = 5? The time (in seconds) that a boot from the NVRAM boot list will delay before starting the boot.
3 PPCBug Firmware Auto Boot Abort Delay = 7? The time in seconds that the Autoboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key. The time value is from 0-255 seconds. (Default = 7 seconds) Auto Boot Default String [NULL for an empty string] = ? You may specify a string (filename) which is passed on to the code being booted. The maximum length of this string is 16 characters.
3 PPCBug Firmware Network Auto Boot at power-up only [Y/N] = N? Y NETboot is attempted at powerup reset only. N NETboot is attempted at any reset. (Default) Network Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User's Manual, listed in Appendix D, Related Documentation for a listing of network controller modules currently supported by PPCBug.
3 PPCBug Firmware Memory Size Ending Address = 02000000? The default Ending Address is the calculated size of local memory. If the memory start is changed from 0x0x00000000, this value will also need to be adjusted. DRAM Speed in NANO Seconds = 15? The default setting for this parameter will vary depending on the speed of the DRAM memory parts installed on the board. The default is set to the slowest speed found on the available banks of DRAM memory.
3 PPCBug Firmware A line feed can be inserted after each code is displayed to prevent it from being overwritten by the next code. This is also enabled by an ENV parameter: The list of LED/serial codes is included in the section on MPU, Hardware, and Firmware Initialization found in Chapter 1 of the PPCBug Firmware Package User’s Manual, listed in Appendix D, Related Documentation. Configuring the VMEbus Interface ENV asks the following series of questions to set up the VMEbus interface for the MVME5100.
3 PPCBug Firmware The configured value is written into the LSI2_BS register of the Universe chip. PCI Slave Image 2 Bound Address Register = A2000000? The configured value is written into the LSI2_BD register of the Universe chip. PCI Slave Image 2 Translation Offset = 500000000? The configured value is written into the LSI2_TO register of the Universe chip. PCI Slave Image 3 Control = C0400000? The configured value is written into the LSI3_CTL register of the Universe chip.
3 PPCBug Firmware VMEbus Slave Image 2 Bound Address Register = 00000000? The configured value is written into the VSI2_BD register of the Universe chip. VMEbus Slave Image 2 Translation Offset = 00000000? The configured value is written into the VSI2_TO register of the Universe chip. VMEbus Slave Image 3 Control = 00000000? The configured value is written into the VSI3_CTL register of the Universe chip.
3 PPCBug Firmware ['NULL' terminates entry]? The Firmware Command Buffer contents contain the BUG commands which are executed upon firmware startup. BUG commands you place into the command buffer should be typed just as you enter the commands from the command line. The string 'NULL' on a new line terminates the command line entries. All PPCBug commands, except for the following, may be used within the command buffer: DU, ECHO, LO, TA, VE.
3 PPCBug Firmware Table 3-1.
3 PPCBug Firmware Table 3-1.
3 PPCBug Firmware Table 3-1.
3 PPCBug Firmware In order to use the diagnostics, you must switch to the diagnostic directory. You may switch between directories by using the SD (Switch Directories) command. You may view a list of the commands in the directory that you are currently in by using the HE (Help) command. If you are in the debugger directory, the debugger prompt PPC6-Bug> is displayed, and all of the debugger commands are available. Diagnostics commands cannot be entered at the PPC6Bug> prompt.
3 PPCBug Firmware Notes 1. You may enter command names in either uppercase or lowercase. 2. Some diagnostics depend on restart defaults that are set up only in a particular restart mode. Refer to the documentation on a particular diagnostic for the correct mode. 3. Test Sets marked with an asterisk (*) are not available on the MVME5100 (unless an IPMC712 or IPMC761 is mounted). The ISABRDGE test is only performed if an IPMC761 is mounted on the MVME5100.
4 Functional Description 4 Introduction This chapter provides a functional description for the MVME5100 Single Board Computer. The MVME5100 is a high-performance product featuring PowerPlus II architecture with a choice of PowerPC processors—either the MPC7410 with AltiVec™ technology for algorithmic intensive computations or the low-power MPC750. The MVME5100 incorporates a highly optimized PCI interface and memory controller enabling up to 582MB memory read bandwidth and 640MB burst write bandwidth.
4 Functional Description Feature Specification Peripheral Support Dual 16550-Compatible Asynchronous Serial Port’s Routed to the Front Panel RJ45 Connnector (COM1) and On-Board Header (COM2) Dual Ethernet Interfaces, one routed to the Front Panel RJ45, One Routed to the Front Panel RJ45 or Optionally Routed to P2, RJ45 on MVME761 VMEbus Tundra Universe Controller, 64-bit PCI Programmable Interrupter & Interrupt Handler Programmable DMA Controller With Link List Support Full System Controller Functions
4 Functional Description 1M,2M Processor MPC7410 MPC750 Clock Generator Mezzanine SDRAM 32MB to 512MB System Registers SDRAM 32MB to 512MB TL16C550 UART/9pin planar Hawk Asic System Memory Controller (SMC) and PCI Host Bridge (PHB) FLASH 1MB to 17MB RTC/NVRAM/WD M48T37V PCI Expansion DEBUG RJ45 33MHz 32/64-bit PCI Local Bus TL16C550 UART Ethernet 1 10/100TX 10/100TX RJ45 10/100TX RJ45 2,64-bit PMC Slots Hawk X-bus Ethernet 2 10/100TX VME Bridge Universe 2 Buffers Front Panel PMC Front
4 Functional Description System Memory Controller and PCI Host Bridge The on-board Hawk ASIC provides the bridge function between the processor’s bus and the PCI bus. It provides 32-bit addressing and 64-bit data; however, 64-bit addressing (dual address cycle) is not supported. The ASIC also supports various processor external bus frequencies up to 100 MHz. There are four programmable map decoders for each direction to provide flexible address mappings between the processor and the PCI bus.
4 Functional Description ECC SDRAM Memory The MVME5100’s on-board memory and optional memory mezzanines allow for a variety of memory size options. Memory size can be 64 or 512MB for a total of 1.5GB on-board and mezzanine ECC memory. The memory is controlled by the hardware which provides single-bit error correction and double-bit error detection (ECC is calculated over 72-bits). Either 1 or 2 mezzanines can be installed. Each mezzanine will add 1 bank of SDRAM memory of 256 or 512MB.
4 Functional Description VMEbus Interface The VMEbus interface is provided by the Universe II ASIC. Refer to the Universe II User’s Manual, as listed in Appendix D, Related Documentation, for additional information. Asynchronous Communications The MVME5100 provides dual asynchronous debug ports. The serial signals COM1 and COM2 are routed through appropriate EIA-232 drivers and receivers to an RJ45 connector on the front panel (COM1) and an on-board connector (COM2).
5 RAM500 Memory Expansion Module 5 Overview The RAM500 memory expansion module can be used on the MVME5100 as an option for additional memory capability. Each expansion module is a single bank of SDRAM with either 256 or 512MB of available ECC memory. Currently, two expansion modules can be used in tandum to produce an additional expanded memory capability of 1GB. There are two configurations of the board to accommodate tandum usage.
5 RAM500 Memory Expansion Module RAM500 Description The RAM500 is a memory expansion module that is used on the MVME5100 Single Board Computer. The RAM500 is based on a single memory mezzanine board design with the flexibility of being populated with different sized SDRAM components and SPD options to provide a variety of memory configurations. The design of the RAM500 allows any memory size module to connect to and operate with any other available memory size module.
5 RAM500 Memory Expansion Module A, BA, WE_L, RAS_L, CAS_L, DQ, CKD DQMB0 CS_C_L SCL SDA A0_SPD CLK1,2 Top-side MVME5100-MEZ Connector CLK3,4 DQMB1 CS_E_L CLK1,2 1 Bank of 9 (x8) SDRAMS SROM SPD Buffer LVTH162244 A, BA, WE_L, RAS_L, CAS_L, DQMB0 CS_C_L DQMB1 CS_E_L DQ, CKD SCL A1_SPD SDA CLK1,2,3,4 Bottom-side MVME5100-MEZ Connector Note: DQMB1, CS_E_L, A1_SPD,CLK3,4 from Bottom Connector is routed to Top connector at the DQMB0, CS_C_L and A0_SPD,CLK1,2 pins. Figure 5-1.
5 RAM500 Memory Expansion Module Host Clock Logic The host board provides four SDRAM clocks to the memory expansion connector. The frequency of the RAM500 CLKS is the same as the host board. RAM500 Module Installation One or more RAM500 memory expansion modules can be mounted on top of the MVME5100 for additional memory capacity. To upgrade or install a RAM500 module, refer to Figure 5-2 and proceed as follows: 1. Attach an ESD strap to your wrist.
5 RAM500 Memory Expansion Module 6. (Optional step) If a second RAM500 module is being used, align the top connector on the bottom RAM500 module with the bottom connector on the top RAM500 module and press the two connectors together until the connectors are seated in place. 7. Insert the three short Phillips screws through the holes at the corners of the RAM500 and screw them into the standoffs. 8.
5 RAM500 Memory Expansion Module Table 5-3. RAM500 Bottom Side Connector (P1)Pin Assignments 48 17 DQ12 DQ13 18 19 DQ14 DQ15 20 21 GND* GND* 22 23 DQ16 DQ17 24 25 DQ18 DQ19 26 27 DQ20 DQ21 28 29 DQ22 DQ23 30 31 +3.3V +3.3V 32 33 DQ24 DQ25 34 35 DQ26 DQ27 36 37 DQ28 DQ29 38 39 DQ30 DQ31 40 41 GND* GND* 42 43 DQ32 DQ33 44 45 DQ34 DQ35 46 47 DQ36 DQ37 48 49 DQ38 DQ39 50 51 +3.3V +3.
5 RAM500 Memory Expansion Module Table 5-3. RAM500 Bottom Side Connector (P1)Pin Assignments 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 +3.3V +3.3V 90 91 CKD06 CKD07 92 93 BA1 BA0 94 95 A12 A11 96 97 A10 A09 98 99 GND* GND* 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 +3.3V +3.3V 110 111 A00 CS_C0_L 112 113 CS_E0_L GND* 114 115 CS_C1_L CS_E1_L 116 117 WE_L RAS_L 118 119 GND* GND* 120 121 CAS_L +3.
5 RAM500 Memory Expansion Module Top Side Memory Expansion Connector (J1) The top side memory expansion connector is a 140-pin AMP 0.6mm Free Height receptacle. This receptacle includes common ground contacts that mate with standard AMP plug assemblies or AMP GIGA assemblies with ground plates. A single memory module will have one bank of SDRAM for a maximum of 512MB of memory. The pin assignments for this connector are as follows: Table 5-4.
5 RAM500 Memory Expansion Module Table 5-4. RAM500 Top Side Connector (J1)Pin Assignments (continued) 59 DQ46 DQ47 60 61 GND* GND* 62 63 DQ48 DQ49 64 65 DQ50 DQ51 66 67 DQ52 DQ53 68 69 +3.3V +3.3V 70 71 DQ54 DQ55 72 73 DQ56 DQ57 74 75 DQ58 DQ59 76 77 DQ60 DQ61 78 79 GND* GND* 80 81 DQ62 DQ63 82 83 CKD00 CKD01 84 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 +3.3V +3.
5 RAM500 Memory Expansion Module Table 5-4. RAM500 Top Side Connector (J1)Pin Assignments (continued) 127 SDA 129 A1_SPD 128 MEZZ2_L 130 GND 132 SDRAMCLK3 134 135 +3.3V 136 137 SDRAMCLK4 138 GND* 140 131 133 139 GND GND* *Common GND pins mate to GIGA assemblies with ground plates. RAM500 Programming Issues The RAM500 contains no user programmable registers, other than the Serial Presence Detect (SPD) Data.
6 Pin Assignments 6 Introduction This chapter provides information on pin assignments for various jumpers and connectors on the MVME5100 Single Board Computer.
6 Pin Assignments Jumper Description J4 Setting Ethernet Port 2 Selection (set in conjunction with jumpers J10 and J17) For “P2” Ethernet Port 2: Pins 1,2; 3,4; 5,6; 7,8 (set for 712/761) For “Front Panel” Ethernet Port 2: No Jumpers Installed J6, J20 Operation Mode (Set Both Jumpers) Pins 1,2 for PMC Mode J7 Flash Memory Selection at Boot Pins 1,2 for Soldered Bank A Ethernet Port 2 Selection (set in conjunction with jumper J4) For “Front Panel” Ethernet Port 2: Pins 1,3 and 2,4 on Both Jumpe
6 Pin Assignments Table 6-1. IPMC761 Connector Pin Assignments (continued) 19 +3.3V DB15# 20 21 DBP1# GND 22 23 GND LANINT2_L 24 25 PIB_INT +3.3V 26 27 +3.3V PIB_PMCREQ# 28 29 PIB_PMCGNT# GND 30 31 GND +3.3V 32 33 +5.0V +5.0V 34 35 GND GND 36 37 +5.0V +5.0V 38 39 GND GND 40 Memory Expansion Connector (J8) Pin Assignments This connector is used to provide memory expansion capability. A single memory mezzanine card provides a maximum of 256MB of memory.
6 Pin Assignments Table 6-2. Memory Expansion Connector Pin Assignments (continued) Pin 56 Assignment Pin 31 +3.3V +3.3V 32 33 DQ24 DQ25 34 35 DQ26 DQ27 36 37 DQ28 DQ29 38 39 DQ30 DQ31 40 41 GND GND 42 43 DQ32 DQ33 44 45 DQ34 DQ35 46 47 DQ36 DQ37 48 49 DQ38 DQ39 50 51 +3.3V +3.3V 52 53 DQ40 DQ41 54 55 DQ42 DQ43 56 57 DQ44 DQ45 58 59 DQ46 DQ47 60 61 GND GND 62 63 DQ48 DQ49 64 65 DQ50 DQ51 66 67 DQ52 DQ53 68 69 +3.3V +3.
6 Pin Assignments Table 6-2. Memory Expansion Connector Pin Assignments (continued) Pin Assignment Pin 97 A10 A09 98 99 GND GND 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 +3.3V +3.3V 110 111 A00 CS_C0_L 112 113 CS_E0_L GND 114 115 CS_C1_L CS_E1_L 116 117 WE_L RAS_L 118 119 GND GND 120 121 CAS_L +3.3V 122 123 +3.
6 Pin Assignments Table 6-3. PCI Expansion Connector Pin Assignments Pin 58 Assignment Pin 1 +3.3V +3.
6 Pin Assignments Table 6-3.
6 Pin Assignments Table 6-3.
6 Pin Assignments Table 6-4.
6 Pin Assignments Table 6-5. PMC Slot 1 Connector (J12) Pin Assignments Pin 62 Assignment Pin 1 +12V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull-up to +3.3V +3.3V 12 13 RST# Pull-down to GND 14 15 +3.3V Pull-down to GND 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 +3.3V 24 25 IDSEL1 AD23 26 27 +3.3V AD20 28 29 AD18 GND 30 31 AD16 C/BE2# 32 33 GND Not Used 34 35 TDRY# +3.
6 Pin Assignments Pin Assignment Pin 1 Reserved GND 2 3 GND C/BE7# 4 5 C/BE6# C/BE5# 6 7 C/BE4# GND 8 9 +5V (Vio) PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 +5V (Vio) AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 +5V (Vio) AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 A
6 Pin Assignments Table 6-6.
6 Pin Assignments Jumper configuration is dependent upon P2 I/O mode chosen (PMC or SBC Mode, also known as 761 or IPMC mode).
6 Pin Assignments Pin Assignment 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull-up to +3.3V +3.3V 12 13 RST# Pull-down to GND 14 15 +3.3V Pull-down to GND 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 +3.3V 24 25 IDSEL2 AD23 26 27 +3.3V AD20 28 29 AD18 GND 30 31 AD16 C/BE2# 32 33 GND Not Used 34 35 TDRY# +3.3V 36 37 GND STOP# 38 39 PERR# GND 40 41 +3.
6 Pin Assignments Pin Assignment Pin 21 +5V (Vio) AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 +5V (Vio) AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 +5V (Vio) AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 63 GND Reserved 64 Pin Assignm
6 Pin Assignments Pin Assignment Pin 35 PMC2_35 (P2-Z23) PMC2_36 (P2-D24) 36 37 PMC2_37 (P2-D25) PMC2_38 (P2-Z25 38 39 PMC2_39 (P2-D26) PMC2_40 (P2-D27) 40 41 PMC2_41 (P2-Z27) PMC2_42 (P2-D28) 42 43 PMC2_43 (P2-D29) PMC2_44 (P2-Z29) 44 45 PMC2_45 (P2-D30) PMC2_46 (P2-Z31) 46 47 Not Used Not Used 48 49 Not Used Not Used 50 51 Not Used Not Used 52 53 Not Used Not Used 54 55 Not Used Not Used 56 57 Not Used Not Used 58 59 Not Used Not Used 60 61 Not Used
6 Pin Assignments Pin Row Z Row A Row B Row C Row D 15 PMC2_23 (J24-23) PMC1_30 (J14-30) VD17 PMC1_29 (J14-29) PMC2_22 (J24-22) 16 GND PMC1_32 (J14-32) VD18 PMC1_31 (J14-31) PMC2_24 (J24-24) 17 PMC2_26 (J24-26) PMC1_34 (J14-34) VD19 PMC1_33 (J14-33) PMC2_25 (J24-25) 18 GND PMC1_36 (J14-36) VD20 PMC1_35 (J14-35) PMC2_27 (J24-27) 19 PMC2_29 (J24-29) PMC1_38 (J14-38) VD21 PMC1_37 (J14-37) PMC2_28 (J24-28) 20 GND PMC1_40 (J14-40) VD22 PMC1_39 (J14-39) PMC2_30 (J24-30)
6 Pin Assignments Pin Row Z Row B Row C Row D 4 GND DB3# VA24 TD+ (10/100) PMC2_6 (J24-6) 5 DB10# DB4# VA25 Not Used PMC2_7 (J24-7) 6 GND DB5# VA26 Not Used PMC2_9 (J24-9) 7 DB11# DB6# VA27 +12VF PMC2_10 (J24-10) 8 GND DB7# VA28 PRSTB# PMC2_12 (J24-12) 9 DB12# DBP# VA29 PRD0 PMC2_13 (J24-13) 10 GND ATN# VA30 PRD1 PMC2_15 (J24-15) 11 DB13# BSY# VA31 PRD2 PMC2_16 (J24-16) 12 GND ACK# GND PRD3 PMC2_18 (J24-18) 13 DB14# RST# +5V PRD4 PMC2_19 (J24-
6 Pin Assignments Pin Row Z Row A Row B Row C Row D 8 GND DB7# VA28 PRSTB# PMC2_12 (J24-12) 9 DB12# DBP# VA29 P DB0 PMC2_13 (J24-13) 10 GND ATN# VA30 P DB1 PMC2_15 (J24-15) 11 DB13# BSY# VA31 P DB2 PMC2_16 (J24-16) 12 GND ACK# GND P DB3 PMC2_18 (J24-18) 13 DB14# RST# +5V P DB4 PMC2_19 (J24-19) 14 GND MSG# VD16 P DB5 PMC2_21 (J24-21) 15 DB15# SEL# VD17 P DB6 PMC2_22 (J24-22) 16 GND D/C# VD18 P DB7 PMC2_24 (J24-24) 17 DBP1# REQ# VD19 P ACK# PMC
6 Pin Assignments Pin Assignment 2 TD- 3 RD+ 4 AC Terminated 5 AC Terminated 6 RD- 7 AC Terminated 8 AC Terminated COM1 and COM2 Connector Pin Assignments A standard RJ45 connector located on the front panel and a 9-pin header located near the bottom edge of the MVME5100 provides the interface to the serial debug ports. The RJ45 connector is for COM1 and the 9-pin header is for COM2.
7 Programming the MVME5100 7 Introduction This chapter provides basic information useful in programming the MVME5100. This includes a description of memory maps, control and status registers, PCI arbitration, interrupt handling, sources of reset and big/little-endian issues. For additional programming information about the MVME5100, refer to the MVME5100-Series Single Board Computer Programmer’s Reference Guide, listed in Appendix D, Related Documentation .
7 Programming the MVME5100 Default Processor Memory Map The default processor memory map that is valid at power-up or reset remains in effect until reprogrammed for specific applications. Table 7-1 defines the entire default map ($00000000 to $FFFFFFFF). Table 7-1.
7 Programming the MVME5100 Processor Memory Map The following table describes a suggested CHRP Memory Map from the point of view of the processor. This memory map is an alternative to the PREP memory map. Note: in all recommended CHRP maps, the beginning of PCI Memory Space is determined by the end of DRAM rounded up to the nearest 256MB-boundry as required by CHRP.
7 Programming the MVME5100 4. The only method to generate a PCI Interrupt Acknowledge cycle (8259 IACK) is to perform a read access to the Hawks PIACK Register at 0xFEFF0030. 5. VME should be placed at the top of PCI memory space. The following table shows the programmed values for the associated Hawk PCI Host Bridge Registers for the suggested Processor Memory Map. Table 7-3. Hawk PPC Register Values for Suggested Memory Map Address Register Name Register Name FEFF 0040 MSADD0 X000 F3FF [X:1..
7 Programming the MVME5100 The Universe PCI/VME bus bridge ASIC includes a user-programmable map decoder for the VMEbus-to-local-bus interface. The address translation capabilities of the Universe enable the processor to access any range of addresses on the VMEbus. Recommendations for VMEbus mapping, including suggested CHRP- and PREP-compatible memory maps, can be found in the MVME5100-Series Single Board Computer Programmer’s Reference Guide.
7 Programming the MVME5100 PROCESSOR VMEBUS PCI MEMORY ONBOARD MEMORY PROGRAMMABLE SPACE NOTE 2 PCI MEMORY SPACE NOTE 1 VME A24 VME A16 NOTE 3 VME A24 VME A16 PCI/ISA MEMORY SPACE NOTE 1 VME A24 VME A16 PCI I/O SPACE VME A24 VME A16 MPC RESOURCES NOTES: 1. Programmable mapping done by Hawk ASIC. 2. Programmable mapping performed via PCI Slave images in Universe ASIC. 3. Programmable mapping performed via Special Slave image (SLSI) in Universe ASIC. Figure 7-1.
7 Programming the MVME5100 Interrupt Handling The Hawk ASIC, which controls the PHB (PCI Host Bridge) and the MPU/local bus interface functions on the MVME5100, performs interrupt handling as well.
7 Programming the MVME5100 The MVME5100 routes the interrupts from the PMCs and PCI expansion slots as follows: PMC Slot 1 INTA# INTB# INTC# INTD# PMC Slot 2 INTA# INTB# INTC# INTD# PCIX Slot INTA# INTB# INTC# INTD# IRQ9 IRQ10 IRQ11 IRQ12 Hawk MPIC DMA Channels The PIB supports seven DMA channels. They are not functional on the MVME5100. Sources of Reset The MVME5100 has nine potential sources of reset: 1. Power-on reset 2. RST switch (resets the VMEbus when the MVME5100 is system controller) 3.
7 Programming the MVME5100 Table 7-5.
7 Programming the MVME5100 PCI Domain The PCI bus is inherently little-endian. All devices connected directly to the PCI bus operate in little-endian mode, regardless of the mode of operation in the processor’s domain. PCI and Ethernet Ethernet is byte-stream-oriented; the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode.
A Specifications A This appendix lists general specifications and power characteristics for the MVME5100 Single Board Computer. It also provides information on cooling requirements. A complete functional description of the MVME5100 Single Board Computer appears in Chapter 4, Functional Description. Specifications for the optional PMC modules can be found in the documentation for those modules. General Specifications The following table lists general specifications for MVME5100 Single Board Computer.
A Specifications Power Requirements Power requirements for the MVME5100 Single Board Computer depend on the configuration of the board. The table below lists the typical and maximum power consumption of the board using an MVME761 Transition Module. Table A-2. Power Consumption Model +5V +/-5% +12V +/-10% -12V +/-10% MVME5100 3.8A max 3.0A typ. 8.0 mA typ. 2.0 mA typ. MVME5106 3.8A max 2.6A typ 8.0 mA typ 2.0 mA typ. MVME5107 4.7 A max. 3.5 A typ. 8.0 mA typ 2.0 mA typ MVME5110-21xx 3.
B Troubleshooting B Solving Startup Problems In the event of difficulty with your MVME5100, perform the simple troubleshooting steps listed in the table below before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment. It is important to note that the Board was tested under these conditions before it left the factory. The self-tests may not run in all user-customized environments. Table B-1.
B Troubleshooting Table B-1. Troubleshooting Problems (continued) Condition Possible Problem Possible Resolution: II. There is a display on the terminal; however, keyboard and/or mouse input has no effect. A. The keyboard or mouse may be connected incorrectly. Recheck the keyboard connections and power. Verify correct configuration of RS232 interface. B. Board jumpers may be configured incorrectly. Check the board jumpers per the instructions in this manual. C.
B Troubleshooting Table B-1. Troubleshooting Problems (continued) Condition Possible Problem IV. Debug prompt 2. At the command line prompt, type in: env;d (this sets up the default parameters for the debugger environment). 3. When prompted to Update Non-Volatile RAM, type in: y 4. When prompted to Reset Local System, type in: y 5. After clock speed is displayed, immediately (within five seconds) press the Return key: -orBREAK to exit to the System Menu.
B Troubleshooting Table B-1. Troubleshooting Problems (continued) Condition Possible Problem Possible Resolution: VI. The board has failed one or more of the tests listed above; cannot be corrected using the steps given. A. There may be some fault in the board hardware or the on-board debugging and diagnostic firmware. 1. Document the problem and return the board for service. 2. Phone 1-800-222-5640.
C Thermal Analysis C Ambient temperature, air flow, board electrical operation and software operation affect board component temperatures. To evaluate the thermal performance of a circuit board assembly, you should test the board under actual operating conditions. These operating conditions vary depending on system design. A thermal analysis was performed in a representative system to verify operation within specified ranges. Refer to Table A-1 in Appendix A, Specifications.
C Thermal Analysis ❏ air - refers to the ambient temperature near the component Table C-1.
C Thermal Analysis Note An MVME5100 Single Board Computer and an IPMC761 I/O board was tested in an Emerson lab environment, and it was verified that the reliability of the components would not be compromised when operating in a maximum ambient temperature of 55 degrees C, if the required airflow of 400 LFM is provided. Customer findings my differ based on specific environmental and operational characteristics.
C Thermal Analysis P15 P14 P12 P13 P11 C10 C8 C7 S1 C9 U12 U11 U7 J3 C5 U6 U5 J2 U4 U3 U19 Y2 U2 C2 Y1 C4 Y3 j1 DS2 DS1 IPMC761 PIB BUSY SCSI BUSY 2844 1100 IPMC761 Figure C-2. Thermally Significant Components on the IPMC761 Module - Primary Side Component Temperature Measurement This section outlines general temperature measurement methods. For the specific types of measurements required for thermal evaluation of this board, see Table C-1.
C Thermal Analysis Allow the board to reach thermal equilibrium before taking measurements. Most circuit boards reach thermal equilibrium within 30 minutes. After the warm up period, monitor a small number of components over time to assure that equilibrium is reached. Measuring Junction Temperature Some components have an on-chip thermal measuring device such as a thermal diode.
C Thermal Analysis Machined groove for thermocouple wire routing Thermocouple junction bonded to component ISOMETRIC VIEW Machined groove for thermocouple wire routing Through hole for thermocouple junction clearance (may require removal of fin material) Also use for alignment guidance during heatsink installation Thermal pad Heatsink base HEATSINK BOTTOM VIEW Figure C-3.
C Thermal Analysis Tape thermocouple wire to top of component Thermocouple junction Air flow PWB Figure C-4.
D Related Documentation D Emerson Network Power - Embedded Computing Documents The Emerson Network Power - Embedded Computing publications listed below are referenced in this manual. You can obtain electronic copies of Emerson Network Power - Embedded Computing publications by contacting your local Emerson sales office. For documentation of final released (GA) products, you can also visit the following website: http://www.emersonnetworkpowerembeddedcomputing.
D Related Documentation Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As an additional help, a source for the listed document is provided. Please note that while these sources have been verified, the information is subject to change without notice. Table D-2.
D Related Documentation Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice. Table D-3. Related Specifications Document Title and Source Publication Number Peripheral Component Interconnect (PCI) Interface Specification, Revision 2.1 PCI Special Interest Group http://www.
Index A Abort (interrupt) signal 13 ABT switch (S1) 13 AltiVec™ technology 38 assembly language 18 Asynchronous Communications 42 Auto Boot Abort Delay 25 Auto Boot Controller 24 Auto Boot Default String 25 Auto Boot Device 24 Auto Boot Partition Number 24 Autoboot enable 24 B backplane connectors, P1 and P2 as power source 5 jumpers 12 baud rate 14 BFL LED 14 BG and IACK signals 12 bit size data/address (MVME5100) 5 bits per character 14 board information block 20 board placement 11 board structure 20 Bo
Index equipment, required 1 Ethernet controller 77 Ethernet Interface 41, 53 Ethernet Interfaces 38 Ethernet PCI controller chips 41 Ethernet Port 2 Configuration 53 Ethernet Port Selection 53 Ethernet ports 37 expansion memory RAM500 43 F Features Description 38 firmware initialization 18 firmware, PPCBug 17 Flash ap note 40 FLASH Memory 37 Flash memory 40 Flash Memory Selection 53 FLASH SMT devices 40 Form Factor 38 front panel controls 13 front panels, using 13 G global bus timeout 5 H hardware confi
Index MVME5100 installing 11 programming 73 mvme5100 description 1 N Negate VMEbus SYSFAIL* Always 23 NETboot enable 25 Network Auto Boot Controller 26 Network Auto Boot enable 25 NIOT debugger command using 26 Non-Volatile RAM (NVRAM) 21 non-volatile static RAM 42 NVRAM 37 NVRAM Bootlist 23 O operation parameter (Auto Boot Abort Delay) 25 parameter (Auto Boot Controller) 24 parameter (Auto Boot Default String) 25 parameter (Auto Boot Device) 24 parameter (Auto Boot Partition Number) 24 parameter (L2 Cac
Index RESET and ABORT Switc 38 resetting the system 13, 80 restart mode 36 Riscwatch Header 53 rogrammable DMA Controller 38 ROM Boot Enable 25 ROMboot enable 25, 27 S SBC mode 38 jumper settings 5 SCSI bus 23 SCSI bus reset on debugger startup 23 SD command 35 SDRAM clocks for RAM500 46 secondary PMCspan installing 9 Secondary SCSI identifier 23 set environment to bug/operating system (ENV) 21 setup terminal 12 SGS-Thomson MK48T559 timekeeper device 80 Soldered Flash Protection 53 sources of reset 80 SPD
