Technical data

Programming Details
MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
59
LBCTL, LALE,
LGPL2
Resistors 101 e500 core
clock PLL ratio
(e500
core:CCB
clock)
000 4:1
001 9:2 (4.5:1)
010 1:1
011 3:2 (1.5:1)
100 2:1
101 5:2 (2.5:1)
110 3:1
111 7:2 (3.5:1)
LGPL3, LGPL5 Fixed 11 Boot
sequencer
configuration
00 Reserved
01 Boot sequencer enabled with
normal I2C address mode
10 Boot sequencer enabled with
extended I2C address mode
11 Boot sequencer disabled
MSRCID0 Fixed 1 Memory
debug
configuration
0 Debug info from the LBC is
driven on MSRCID and MDVAL
pins
1 Debug info from the DDR
SDRAM controller is driven on
MSRCID and MDVAL pins
MSRCID1 Fixed 1 DDR debug
configuration
0 Debug info on ECC pins
instead of normal ECC
1 ECC pins function in normal
mode
Table 4-1 MPC8548E POR Configuration Settings (continued)
MPC8548E
Signal
Select
Option
Default
POR
Setting Description State of Bit vs. Function