Technical data

Programming Details
MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
57
TSEC3_TXD[0],
TSEC3_TXD[1]
Fixed 10 TSEC3
protocol
configuration
00 TSEC3 controller uses 16-bit
FIFO mode (8-bit FIFO mode if
TSEC3 configured in reduced
mode
01 TSEC3 controller uses MII
protocol (RMII id TSEC3
configured in reduced mode)
10 TSEC3 controller uses GMII
protocol (RGMII if TSEC3
configured in reduced mode)
11 TSEC3 controller uses TBI
protocol (RTBI if TSEC3
configured in reduced mode)
TSEC3_TXD[2] Fixed 0 TSEC 3 and 4
configuration
width
0 TSEC 3 and 4 in reduced mode
(RTBI or RGMII)
1 TSEC 3 and 4 in standard
mode (TBI or GMII)
TSEC4_TXD[0],
TSEC4_TXD[7]
Fixed 10 TSEC4
protocol
configuration
00 Reserved
01 TSEC4 controller uses RMII
protocol
10 TSEC3 controller uses RGMII
protocol
11 TSEC3 controller uses RTBI
protocol
TSEC4_TXD[2] Fixed 1 SerDes enable 0 SerDes interface is disabled
1 SerDes interface is enabled
LA[27] Fixed 1 CPU boot
configuration
0 CPU boot hold off mode
1 e500 core boots without
waiting for configuration by
an external master
Table 4-1 MPC8548E POR Configuration Settings (continued)
MPC8548E
Signal
Select
Option
Default
POR
Setting Description State of Bit vs. Function