Technical data

MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)

3.1.20 Watch Dog Timer Count Register

The MVME4100 provides a watch dog timer count register.

10: 2 ms

11: 4 ms

12: 8 ms

13: 16 ms

14: 32 ms

15: 64 ms

RSVD Reserved for future implementation.

Table 3-23 Watch Dog Timer Count Register

REG Watch Dog Timer Counter Register - 0xF200 0026

BIT 15:0

Field Count

OPER R/W

RESET 03FF

COUNT Count. These bits define the watch dog timer count value. When the watch dog counter is

enabled or there is a write to the load register, the watch dog counter is set to the count

value. When enabled the watch dog counter will decrement at a rate defined by the

resolution register. The counter will continue to decrement until it reaches zero or the

software writes to the load register. If the counter reaches zero a system or board-level

reset will be generated.