Technical data

Register Descriptions
MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
34
3.1.6 Interrupt Register 2
The RTC, TEMP sensor and Abort switch interrupts are OR'd together. The MVME4100 provides
an Interrupt Register that may be read by the system software to determine which device
originated the interrupt. This register also includes bits that allow the interrupt sources to be
mask.
Table 3-7 Interrupt Register 2
REG Interrupt Register 2 - 0xF200 0005
BIT76543210
Field RSVD RTC
Mask
TEMP
Mask
ABORT
Mask
RSVD RTC
Status
TEMP
Status
ABORT
Status
OPER R R/W R
RESET01110XX0
ABORT Status ABORT Status. This bit reflects the current state of the on-board abort signal. This is a
debounced version of the abort switch and may be used to determine the state of the
abort switch. A cleared condition indicates that the abort switch is not depressed while
a set condition indicates that the abort switch is asserted.
TEMP Status TEMP Status. If cleared, the Temperature sensor output is not asserted. If set, the
Temperature sensor output is asserted.
RTC Status RTC Status. If cleared, the RTC output is not asserted. If set, the RTC output is asserted.
ABORT Mask ABORT Mask. This bit is used to mask the abort switch output. If this bit is cleared, the
abort switch output is enabled to generate an interrupt. If the bit is set, the abort switch
output is disabled from generating an interrupt.
TEMP Mask TEMP Mask. This bit is used to mask the MAX6649 temperature sensor thermostat
output. If this bit is cleared, the thermostat output is enabled to generate an interrupt. If
the bit is set, the thermostat output is disabled from generating an interrupt.
RTC Mask RTC Mask. This bit is used to mask the RTC output. If this bit is cleared, the RTC output is
enabled to generate an interrupt. If the bit is set, the RTC output is disabled from
generating an interrupt.
RSVD Reserved for future implementation.