Technical data

Register Descriptions
MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)
33
3.1.5 Interrupt Register 1
The MVME4100 provides an Interrupt Register that may be read by the system software to
determine which of the Ethernet PHYs originated their combined (OR'd) interrupt
Table 3-6 Interrupt Register 1
REG Interrupt Register 1 - 0xF200 0004
BIT76543210
Field RSVD RSVD RSVD RSVD PHY4 PHY3 PHY2 PHY1
OPER R
RESET00000000
PHY1 TSEC1 PHY Interrupt. If cleared, the TSEC1 interrupt is not asserted. If set, the TSEC1
interrupt is asserted.
PHY2 TSEC2 PHY Interrupt. If cleared, the TSEC2 interrupt is not asserted. If set, the TSEC2
interrupt is asserted.
PHY3 TSEC3 PHY Interrupt. If cleared, the TSEC3 interrupt is not asserted. If set, the TSEC4
interrupt is asserted.
PHY4 TSEC4 PHY Interrupt. If cleared, the TSEC4 interrupt is not asserted. If set, the FEC interrupt
is asserted.
RSVD Reserved for future implementation.