Technical data

Chapter 3

MVME4100 Single Board Computer Programmer’s Reference (6806800H19B)

3.1 Overview

System resources including system control and status registers, external timers, and the

QUART are mapped into a 16 MB address range accessible from the MVME4100 local bus via

the MPC8548E LBC. The memory map is defined in the following table including the LBC bank

chip select used to decode the register.

Any address that is not listed in the table blelow is unused and reserved for future use.

Table 3-1 System I/O Memory Map

Address Definition

LBC Bank/Chip

Select Notes

F200 0000 System Status Register 4 3

F200 0001 System Control Register 4 3

F200 0002 Status Indicator Register 4 3

F200 0003 NOR Flash Control/Status Register 4 3

F200 0004 Interrupt Register 1 4 3

F200 0005 Interrupt Register 2 4 3

F200 0006 Presence Detect Register 4 3

F200 0008 PCI Bus Status Register 1 4 3

F200 0009 PCI Bus Status Register 2 4 3

F200 000A PCI Bus Status Register 3 4 3

F200 0010 NAND Flash Chip 1 Control Register 4 3

F200 0011 NAND Flash Chip 1 Select Register 4 3

F200 0012 Reserved 4 1

F200 0013 Reserved 4 1

F200 0014 NAND Flash Chip 1 Presence Register 4 3

F200 0015 NAND Flash Chip 1 Status Register 4 3