User's Manual

ManualsBrandsEmerson ManualsComputer equipmentMVME3100

Embedded Computing for

Business-Critical Continuity

MVME3100 Single Board Computer

Installation and Use

P/N: 6806800M28C

December 2012

Summary of content (156 pages)

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Embedded Computing for Business-Critical ContinuityTM MVME3100 Single Board Computer Installation and Use P/N: 6806800M28C December 2012
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© 2011 Emerson All rights reserved. Trademarks Emerson, Business-Critical Continuity, Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co. © 2008 Emerson Electric Co. All other product or service names are the property of their respective owners. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
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Contents About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1 1.2 1.3 1.4 1.5 1.6 2 Startup and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.1 2.2 2.
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Contents Contents 3.5.2 Control Register/Control Status Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5.3 Displaying VME Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5.4 Editing VME Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.5.5 Deleting VME Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 4.11 4.12 4.13 4.14 5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 5.2 5.3 6 4.10.5 PCI Mezzanine Card Slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.10.6 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.
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Contents Contents 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 Flash Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PCI Bus Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Interrupt Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Presence Detect Register . .
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Contents A.2 A.3 B Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Thermally Significant Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 B.1 B.2 B.
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Contents Contents 8 MVME3100 Single Board Computer Installation and Use (6806800M28C)
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List of Tables Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 2-1 Table 2-2 Table 2-3 Table 3-1 Table 3-2 Table 4-1 Table 4-2 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Table 5-17 Table 5-18 Table 6-1 Table 6-2 Table 6-3 Startup Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Table 6-9 Table 6-10 Table 6-11 Table 6-12 Table 6-13 Table 6-14 Table 6-15 Table 6-16 Table 6-17 Table 6-18 Table 6-19 Table 6-20 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table A-1 Table A-2 Table A-3 Table B-1 Table B-2 Table B-3 10 System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures Figure 1-1 Figure 1-2 Figure 2-1 Figure 4-1 Figure 4-2 Figure A-1 Figure A-2 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Geographical Address Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Front Panel LEDs and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 MVME3100 Block Diagram . . . . . . . . . . . . . . .
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List of Figures 12 MVME3100 Single Board Computer Installation and Use (6806800M28C)
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About this Manual Overview of Contents This manual is divided into the following chapters and appendices: Hardware Preparation and Installation, provides MVME3100 board preparation and installation instructions, as well as ESD precautionary notes. Startup and Operation, provides the power-up procedure and identifies the switches and indicators on the MVMEM3100. MOTLoad Firmware, describes the basic features of the MOTLoad firmware product.
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About this Manual About this Manual As of the printing date of this manual, the MVME3100 supports the models listed below.
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About this Manual Abbreviation Description DUART Dual Universal Asynchronous Receiver/Transmitter ECC Error Correction Code ENET Ethernet ENV Environment ESD Electrostatic Discharge FAT File Allocation Table FEC Fast Ethernet Controller FIFO First In First Out FPU Floating Point Unit GA Geographic Address GENET Gigabit Ethernet GEV Global Environment Variable GMII Gigabit Media Independent Interface GPCM General Purpose Chip select Machine IBCA Inter-Board Communication Addre
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About this Manual About this Manual Abbreviation Description NVRAM Non Volatile RAM OS Operating System PAL Physical Abstraction Layer PCB Printed Circuit Board PCI Peripheral Connect Interface PCI-X Peripheral Component Interconnect -X PHY Physical Layer PIC Programmable Interrupt Controller PIM PCI Mezzanine Card Input/Output Module PLD Programmable Logic Device PMC PCI Mezzanine Card (IEEE P1386.
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About this Manual Abbreviation Description TSOP Thin Small Outline Package UART Universal Asynchronous Receiver/Transmitter UNIX UNIX operating system USB Universal Serial Bus VIO Input/Output Voltage VITA VMEbus International Trade Association VME VersaModule Eurocard VMEbus VersaModule Eurocard bus VPD Vital Product Data WP Write Protect Conventions The following table describes the conventions used throughout this manual.
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About this Manual About this Manual Notation Description ... Repeated item for example node 1, node 2, ..., node 12 . Omission of information from example/command that is not necessary at the time being . . .. Ranges, for example: 0..
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About this Manual Summary of Changes This manual has been revised and replaces all prior editions. Part Number Publication Date Description 6806800M28C December 2012 Added Declaration of Conformity on page 22. 6806800M28B August 2011 Updated Safety Notes on page 148 and Sicherheitshinweise on page 152.
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About this Manual About this Manual 20 MVME3100 Single Board Computer Installation and Use (6806800M28C)
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Chapter 1 Hardware Preparation and Installation 1.1 Overview The MVME3100 is a single-slot, single-board computer based on the MPC8540 PowerQUICC III™ integrated processor. The MVME3100 provides serial ATA (sATA), USB 2.0, 2eSST VMEbus interfaces, dual 64-bit/100 MHz PMC sites, up to 128MB of Flash, dual 10/100/1000 Ethernet, one 10/100 Ethernet, and five serial ports. This board supports front and rear I/O and a single SODIMM module for DDR memory.
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Hardware Preparation and Installation Table 1-1 Startup Overview (continued) What you need to do... Refer to... Connect any other equipment you will be using Connecting to Peripherals on page 31 Verify the hardware is installed. Completing the Installation on page 33 1.2.2 Unpacking Guidelines Unpack the equipment from the shipping carton. Refer to the packing list and verify that all items are present. Save the packing material for storing and reshipping of equipment.
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Hardware Preparation and Installation Most options on the MVME3100 are software configurable. Configuration changes are made by setting bits in control registers after the board is installed in a system. Jumpers/switches are used to control those options that are not software configurable. These jumper settings are described further on in this section. If you are resetting the board jumpers from their default settings, it is important to verify that all settings are reset properly. 1.4.
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Hardware Preparation and Installation The MVME3100 is factory tested and shipped with the configuration described in the following sections.
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Hardware Preparation and Installation Figure 1-1 Board Layout J25 J24 J28 U1014 U1049 S4 1 U1050 J30 J21 J22 U1020 U1019 U1052 S3 U1026 1 U1046 U1047 U1027 U5000 U1051 P1 J23 U1025 J11 J12 J13 J14 U21 U1003 U1007 U1010 J2 U1012 U1024 U1012 P2 U1000 J4 MVME3100 Single Board Computer Installation and Use (6806800M28C) 25
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Hardware Preparation and Installation 1.4.2 Configuration Switch (S4) An 8-position SMT configuration switch controls the VME SCON setting, Flash bank writeprotect, and the safe start ENV settings. It also selects the Flash boot image. The default setting on all switch positions is OFF. Table 1-2 Configuration Switch (S4) Settings Setting Switch Pos. OFF (Factory Default) ON Notes SAFE_START 1 Normal ENV settings should be used. Safe ENV settings should be used.
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Hardware Preparation and Installation Table 1-2 Configuration Switch (S4) Settings (continued) Setting Switch Pos. OFF (Factory Default) ON Notes TRST SELECT 8 Normal MPC8540 TRST mode where the board HRESET will assert TRST. Isolates the board HRESET from TRST and allows the board to reset without resetting the MPC8540 JTAG/COP interface. This switch should remain in the OFF position unless a MPC8540 emulator is attached. 1.4.
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Hardware Preparation and Installation Table 1-3 Geographical Address Switch Assignments (continued) Position SW1 SW21 SW3 SW4 SW5 SW6 SW7 SW8 Factory Setting (Default) OFF OFF PCI mode OFF 1 OFF 1 OFF 1 OFF 1 OFF 1 OFF 1 Note: 1SW2 has been configured to work in PCI-X mode only. The default setting is OFF.
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Hardware Preparation and Installation Table 1-4 Slot Geographical Address Settings (continued) Slot Address GAP GA(4:0) SW3 SW4 SW5 SW6 SW7 SW8 20 0 01011 ON ON OFF ON OFF OFF 21 1 01010 OFF ON OFF ON OFF ON 1.4.4 PMC I/O Voltage Configuration The onboard PMC sites may be configured to support 3.3V or 5.0V I/O PMC modules. To support 3.3V or 5.0V I/O PMC modules, both PMC I/O keying pins must be installed in the holes.
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Hardware Preparation and Installation Table 1-6 EEPROM Address Settings (continued) Device Address A(2:0) SW1 SW2 SW3 $AC 110 ON OFF OFF $AE 111 OFF OFF OFF The RTM EEPROM address switches must be set for address $AA in order for this device to be accessible by MotLoad. 1.5 Installing Hardware Damage of the Product and Additional Devices and Modules z Incorrect installation or removal of additional devices or modules may damage the product or the additional devices or modules.
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Hardware Preparation and Installation Procedure Use the following steps to install the MVME3100 into your computer chassis. 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to an electrical ground (refer to Unpacking Guidelines). The ESD strap must be secured to your wrist and to ground throughout the procedure. 2. Remove any filler panel that might fill that slot. 3. Install the top and bottom edge of the MVME3100 into the guides of the chassis. 4.
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Hardware Preparation and Installation Figure 1-1 on page 25 shows the locations of the various connectors while Table 1-7 and Table 1-8 list them for you. Refer to Chapter 5, Pin Assignments for the pin assignments of the connectors listed below. Damage of the Product and Additional Devices and Modules z Incorrect installation or removal of additional devices or modules damages the product or the additional devices or modules.
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Hardware Preparation and Installation Table 1-8 MVME721 Rear Transition Module Connectors (continued) Connector Function J2A 10/100/1000Mb/s Ethernet connector J2B 10/100Mb/s Ethernet connector J10 PIM power/ground J14 PIM I/O P2 VME backplane connector 1.7 Completing the Installation Verify that hardware is installed and the power/peripheral cables connected are appropriate for your system configuration.
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Hardware Preparation and Installation 34 MVME3100 Single Board Computer Installation and Use (6806800M28C)
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Chapter 2 Startup and Operation 2.1 Introduction This chapter gives you information about the: 2.2 z Power-up procedure z Runtime switches and indicators Applying Power After you verify that all necessary hardware preparation is complete and all connections are made correctly, you can apply power to the system. When you are ready to apply power to the MVME3100: 2.
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Startup and Operation Table 2-1 Front-Panel LED Status Indicators (continued) Function Label Color Description GENET 1 Link / Speed SPEED Off No link Yellow 10/100Base-T operation Green 1000Base-T operation Blinking Green Activity proportional to bandwidth utilization.
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Startup and Operation Figure 2-1 Front Panel LEDs and Connectors PMC 2 PMC 1 SATA 1 ABORT/RESET USER 1 COM 1 G ENET 1 FAIL SPEED ACT MVME3100 Single Board Computer Installation and Use (6806800M28C) 37
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Startup and Operation The MVME721 rear transition module also has four status indicators. The following table describes these indicators: Table 2-2 MVME721 LED Status Indicators Function Label Color Description GENET 2 Link/Speed SPEED Off No link Yellow 10/100Base-T operation Green 1000Base-T operation Blinking Green Activity proportional to bandwidth utilization. Off No activity Off No link Yellow 10/100Base-T operation Blinking Green Activity proportional to bandwidth utilization.
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Startup and Operation Table 2-3 Additional Onboard Status Indicators (continued) Function Label Color Description MPC8540 Ready DS3 (silkscreen) Green Indicates that the MPC8540 has completed the reset operation and is not in a power-down state. The MPC8540 Ready is multiplexed with the MPC8540 TRIG_OUT so the LED can be programmed to indicate one of three trigger events based on the value in the MPC8540 TOSR register.
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Startup and Operation 40 MVME3100 Single Board Computer Installation and Use (6806800M28C)
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Chapter 3 MOTLoad Firmware 3.1 Overview The MOTLoad firmware package serves as a board power-up and initialization package, as well as a vehicle from which user applications can be booted. A secondary function of the MOTLoad firmware is to serve in some respects as a test suite providing individual tests for certain devices. This chapter includes a list of standard MOTLoad commands, the default VME and firmware settings that are changeable by the user, remote start, and the alternate boot procedure.
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MOTLoad Firmware Operationally, MOTLoad utility applications differ from MOTLoad test applications in several ways: 3.3.2 z Only one utility application operates at any given time (that is, multiple utility applications cannot be executing concurrently) z Utility applications may interact with the user. Most test applications do not. Tests A MOTLoad test application determines whether or not the hardware meets a given standard. Test applications are validation tests.
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MOTLoad Firmware Most MOTLoad tests can be organized to execute as a group of related tests (a testSuite) through the use of the testSuite command. The expert operator can customize their testing by defining and creating a custom testSuite(s). The list of built-in and user-defined MOTLoad testSuites, and their test contents, can be obtained by entering testSuite -d at the MOTLoad prompt. All testSuites that are included as part of a product specific MOTLoad firmware package are product specific.
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description bmb Block Move Byte/Halfword/Word bmh bmw br Assign/Delete/Display User-Program Break-Points bsb Block Search Byte/Halfword/Word bsh bsw bvb Block Verify Byte/Halfword/Word bvh bvw cdDir ISO9660 File System Directory Listing cdGet ISO9660 File System File Load clear Clear the Specified Status/History Table(s) cm Turns on Concurrent Mode csb Calculates a Checksum Specified by Command-line Options csh csw devShow
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description fdShow Display (Show) File Discriptor flashLock Flash Memory Sector Lock flashProgram Flash Memory Program flashShow Display Flash Memory Device Configuration Data flashUnlock Flash Memory Sector Unlock gd Go Execute User-Program Direct (Ignore Break-Points) gevDelete Global Environment Variable Delete gevDump Global Environment Variable(s) Dump (NVRAM Header + Data) gevEdit Global Environment Variable Edit gevI
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description mpuShow Display multi-processor control structure mpuStart Start the other MPU netBoot Network Boot (BOOT/TFTP) netShow Display Network Interface Configuration Data netShut Disable (Shutdown) Network Interface netStats Display Network Interface Statistics Data noCm Turns off Concurrent Mode pciDataRd Read PCI Device Configuration Header Register pciDataWr Write PCI Device Configuration Header Register pciDump D
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description testDisk Test Disk testEnetPtP Ethernet Point-to-Point testNvramRd NVRAM Read testNvramRdWr NVRAM Read/Write (Destructive) testRam RAM Test (Directory) testRamAddr RAM Addressing testRamAlt RAM Alternating testRamBitToggle RAM Bit Toggle testRamBounce RAM Bounce testRamCodeCopy RAM Code Copy and Execute testRamEccMonitor Monitor for ECC Errors testRamMarch RAM March testRamPatterns RAM Patterns testRamPe
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MOTLoad Firmware Table 3-1 MOTLoad Commands (continued) Command Description tftpPut TFTP Put time Display Date and Time transparentMode Transparent Mode (Connect to Host) tsShow Display Task Status upLoad Up Load Binary Data from Target version Display Version String(s) vmeCfg Manages user specified VME configuration parameters vpdDisplay VPD Display vpdEdit VPD Edit wait Wait for Test Completion waitProbe Wait for I/O Probe to Complete 3.
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MOTLoad Firmware MVME3100> mytest "mytest" not found MVME3100> If the user enters a partial MOTLoad command string that can be resolved to a unique valid MOTLoad command and presses the carriage-return key, the command will be executed as if the entire command string had been entered. This feature is a user-input shortcut that minimizes the required amount of command line input. MOTLoad is an ever changing firmware package, so user-input shortcuts may change as command additions are made.
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MOTLoad Firmware 3.4.
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MOTLoad Firmware Usage: testRam [-aPh] [-bPh] [-iPd] [-nPh] [-tPd] [-v] Description: RAM Test [Directory] Argument/Option Description -a Ph: Address to Start (Default = Dynamic Allocation) -b Ph: Block Size (Default = 16KB) -i Pd: Iterations (Default = 1) -n Ph: Number of Bytes (Default = 1MB) -t Ph: Time Delay Between Blocks in OS Ticks (Default = 1) -v O : Verbose Output MVME3100> 3.
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MOTLoad Firmware The VMEbus Master Control Register is set to the default (RESET) condition. z MVME3100> vmeCfg –s –r238 Displaying the selected Default VME Setting - interpreted as follows: VMEbus Control Register = 00000008 MVME3100> The VMEbus Control Register is set to a Global Timeout of 2048 μseconds.
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MOTLoad Firmware Inbound window 0 (ITAT0) is not enabled; Virtual FIFO at 256 bytes, 2eSST timing at SST320, respond to 2eSST, 2eVME, MBLT, and BLT cycles, A32 address space, respond to Supervisor, User, Program, and Data cycles. Image maps from 0x00000000 to 0x1FFF0000 on the VMbus, translates 1x1 to the PCI-X bus (thus 1x1 to local memory). To enable this window, set bit 31 of ITAT0 to 1.
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MOTLoad Firmware Outbound Image 2 Translation Offset Upper Register = 00000000 Outbound Image 2 Translation Offset Lower Register = 40000000 Outbound Image 2 2eSST Broadcast Select Register = 00000000 MVME3100> Outbound window 2 (OTAT2) is enabled, 2eSST timing at SST320, transfer mode of SCT, A24/D32 Supervisory access.
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MOTLoad Firmware Outbound Image 7 Translation Offset Upper Register = 00000000 Outbound Image 7 Translation Offset Lower Register = 4F000000 Outbound Image 7 2eSST Broadcast Select Register = 00000000 MVME3100> Outbound window 7 (OTAT7) is enabled, 2eSST timing at SST320, transfer mode of SCT, CR/CSR Supervisory access.
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MOTLoad Firmware 3.5.
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MOTLoad Firmware 3.5.5 Deleting VME Settings To delete the changeable VME setting (restore default value), type the following at the firmware prompt: 3.5.
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MOTLoad Firmware 3.6 Remote Start As described in the MOTLoad Firmware Package User's Manual, listed in Appendix B, Related Documentation, remote start allows the user to obtain information about the target board, download code and/or data, modify memory on the target, and execute a downloaded program. These transactions occur across the VMEbus in the case of the MVME3100.
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MOTLoad Firmware Mailbox 0 is at offset 7f348 in the CR/CSR space Mailbox 1 is at offset 7f34C in the CR/CSR space Mailbox 2 is at offset 7f350 in the CR/CSR space Mailbox 3 is at offset 7f354 in the CR/CSR space The selection of the mailbox used by remote start on an individual MVME3100 is determined by the setting of a global environment variable (GEV). The default mailbox is zero. Another GEV controls whether remote start is enabled (default) or disabled.
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MOTLoad Firmware z If a valid USER boot image is not found, search the active flash bank, possibly interactively, for a valid MCG boot image; anticipated to be upgrade of MCG firmware. If found, the image is executed. A return to the boot block code is not anticipated.
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MOTLoad Firmware The scan is performed downwards from boot block image and searches first for POST, then USER, and finally MCG images. In the case of multiple images of the same type, control is passed to the first image encountered in the scan. Safe Start, whether invoked by hitting ESC on the console within the first five seconds following power-on reset or by setting the Safe Start jumper, interrupts the scan process. The user may then display the available boot images and select the desired image.
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MOTLoad Firmware 3.10 Boot Images Valid boot images whether POST, USER, or MCG, are located on 1MB boundaries within flash. The image may exceed 1MB in size. An image is determined valid through the presence of two "valid image keys" and other sanity checks.
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MOTLoad Firmware startPtr++; } return(checksum); } 3.10.2 Image Flags The image flags of the header define various bit options that control how the image will be executed.
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MOTLoad Firmware z DONT_AUTO_RUN If set, this flag indicates that the image is not to be selected for automatic execution. A user, through the interactive command facility, may specify the image to be executed. MOTLoad currently uses an Image Flag value of 0x3, which identifies itself as an Alternate MOTLoad image that executes from RAM. MOTLoad currently does not support execution from flash. 3.10.3 User Images These images are user-developer boot code; for example, a VxWorks bootrom image.
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MOTLoad Firmware 3.10.4 Alternate Boot Data Structure The globalData field of the alternate boot data structure points to an area of RAM which was initialized to zeroes by the boot loader. This area of RAM is not cleared by the boot loader after execution of a POST image, or other alternate boot image, is executed. It is intended to provide a user a mechanism to pass POST image results to subsequent boot images.
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MOTLoad Firmware 3.10.6 Boot Image Firmware Scan The scan is performed by examining each 1 MB boundary for a defined set of flags that identify the image as being POST, USER, or Alternate MOTLoad. POST is a user-developed Power On Self Test that would perform a set of diagnostics and then return to the boot loader image. USER would be a boot image, such as the VxWorks bootrom, which would perform board initialization. A bootable VxWorks kernel would also be a USER image.
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MOTLoad Firmware 'h':this help screen boot> d Addr FFE00000 Size 00100000 Flags 00000003 Name: MOTLoad Addr FFD00000 Size 00100000 Flags 00000003 Name: MOTLoad boot> c NOPQRSTUVabcdefghijk#lmn3opqrsstuvxyzaWXZ Copyright Motorola Inc. 1999-2004, All Rights Reserved MOTLoad RTOS Version 2.0, PAL Version 0.b EA02 ... MVME3100> 3.
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MOTLoad Firmware 68 MVME3100 Single Board Computer Installation and Use (6806800M28C)
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Chapter 4 Functional Description 4.1 Overview This chapter describes the MVME3100 and the MVME721 rear transition module (RTM) on a block diagram level. 4.2 Features The following tables list the features of the MVME3100 and its RTM.
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Functional Description Table 4-1 MVME3100 Features Summary (continued) Feature Description PCI Interface Bus A: — 66 MHz PCI-X mode — One TSi148 VMEbus controller — One serial ATA (sATA) controller — One MPC8540 — Two PCI6520 PCI-X-to-PCI-X bridges (primary side) Bus B: — 33/66/100 MHz PCI/PCI-X (PCI 2.2 and PCI-X 1.0b compliant) — Two +3.
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Functional Description Table 4-1 MVME3100 Features Summary (continued) Feature Description Serial Interface — One 16550-compatible, 9.6 to 115.2 KBAUD, MPC8540, asynchronous serial channel for front-panel I/O — One quad UART controller to provide four 16550-compatible, 9.6 to 115.
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Functional Description Table 4-2 MVME721 RTM Features Summary (continued) Feature Description Miscellaneous — Four status indicators: 10/100/1000 and 10/100 Ethernet link/speed and activity LEDs 72 MVME3100 Single Board Computer Installation and Use (6806800M28C)
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Functional Description 4.3 Block Diagrams Figure 4-1 shows a block diagram of the overall board architecture and Figure 4-2 shows a block diagram of the MVME721 rear transition module architecture.
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Functional Description Figure 4-2 MVME721 RTM Block Diagram Rear Panel Future Option U S B PIM 10 GigE RJ45 sATA 10/100 RJ45 Serial RJ45 Serial RJ45 Serial RJ45 Serial RJ45 PIM GigE 2 10/100 PMC 1 Jn4 10 Serial Port 4 Serial Port 3 Serial Port 2 Serial Port 1 VPD 8K8 sATA 3 USB 2 I2C Bus P2 P0 Future Option 4390 0106 4.4 Processor The MVME3100 supports the MPC8540 processor. The processor core frequency runs at 833 or 667 MHz. The MPC8540 has integrated 256KB L2 cache. 4.
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Functional Description 4.6 Local Bus Interface The MVME3100 uses the MPC8540 local bus controller (LBC) for access to on-board Flash and I/O registers. The LBC has programmable timing modes to support devices of different access times, as well as device widths of 8, 16, and 32 bits. The MVME3100 uses the LBC in GPCM (general purpose chip select machine) mode to interface to two physical banks of on-board Flash, an on-board quad UART (QUART), on-board 32-bit timers, and the System Control/Status registers.
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Functional Description 4.
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Functional Description A Broadcom BCM5221 PHY is used for the FEC interface. The Fast Ethernet interface is routed to P2 for rear I/O. Isolation transformers are provided on-board for each interface. The assigned PHY addresses for the MPC8540 MII management (MIIM) interface can be found in the MVME3100 Single-Board Computer Programmer’s Reference Guide, listed in Appendix B, Related Documentation. Each Ethernet interface is assigned an Ethernet Station Address. The address is unique for each device.
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Functional Description 4.10.2 TSi148 VME Controller The VMEbus interface for the MVME3100 is provided by the TSi148 ASIC. The TSi148 provides the required VME, VME extensions, and 2eSST functions. Transceivers are used to buffer the VME signals between the TSi148 and the VME backplane. Refer to the TSi148 User's Manual listed in Appendix B, Related Documentation, for additional details and/or programming information. 4.10.
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Functional Description 4.10.5 PCI Mezzanine Card Slots The MVME3100 provides two PMC sites that support standard PMCs or PrPMCs. Both PMC sites are located on PCI bus B and operate at the same speed and mode as determined by the slowest PMC module. The board routing supports a maximum of 100 MHz PCI-X operation on each site. Signaling voltage (Vio) for the two PMC sites is dependent on keying pin installation options and can be configured for 5V or 3.3V.
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Functional Description In this case, the MVME3100 supports: Feature Description Mezzanine Type: PMC = PCI Mezzanine Card Mezzanine Size: Double width and standard depth (150mm x 150mm) with front panel PMC Connectors: J11, J12, J13, J14, J21, J22, and J23 (32/64-bit PCI with front and rear I/O) on J14 only Signaling Voltage: VIO = +3.
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Functional Description 4.11 General-Purpose Timers There are a total of eight independent, 32-bit timers. Four timers are integrated into the MPC8540 and four timers are in the PLD. The four MPC8540 timers are clocked by the RTC input, which is driven by a 1 MHz clock. The clock source for the four timers in the PLD is 25 MHz. Refer to the MPC8540 Reference Manual listed in Appendix B, Related Documentation, for additional details and/or programming information. 4.
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Functional Description 4.14 Debug Support The MVME3100 provides a boundary scan header for boundary scan test access and device programming. This board also provides a separate standard COP header for MPC8540 COP emulation.
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Chapter 5 Pin Assignments 5.1 Overview This chapter provides pin assignments for various connectors and headers on the MMVE3100 single-board computer and the MVME721 transition module.
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Pin Assignments 5.2.1 PMC Expansion Connector (J4) One 114-pin Mictor connector with a center row of power and ground pins is used to provide PCI expansion capability. The pin assignments for this connector are as follows: Table 5-1 PMC Expansion Connector (J4) Pin Assignments Pin Signal Signal Pin 1 +3.3V +3.
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Pin Assignments Table 5-1 PMC Expansion Connector (J4) Pin Assignments (continued) Pin Signal Signal Pin 39 PAR PCIRST# 40 41 C/BE1# C/BE0# 42 43 C/BE3# C/BE2# 44 45 AD1 AD0 46 47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 +5V MVME3100 Single B
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Pin Assignments Table 5-1 PMC Expansion Connector (J4) Pin Assignments (continued) Pin Signal Signal Pin 77 PAR64 No Connect 78 79 C/BE5# C/BE4# 80 81 C/BE7# C/BE6# 82 83 AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD6
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Pin Assignments 5.2.2 Ethernet Connectors (GENET1/J41B, GENET2/J2B, ENET1/J2A) There is one 10/100 and two 10/100/1000Mb/s full duplex Ethernet interfaces using the MPC8540 Fast Ethernet Controller (FEC) and two Triple Speed Ethernet Controllers (TSEC). One Gigabit Ethernet interface is routed to a front-panel RJ-45 connector with integrated LEDs for speed and activity indication. The other Gigabit Ethernet interface and the 10/100 interface are routed to P2 for rear I/O.
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Pin Assignments Table 5-3 PMC Slot 1 Connector (J11) Pin Assignments (continued) Pin Signal Signal Pin 7 PMCPRSNT1# +5V 8 9 INTD# PCI_RSVD 10 11 GND +3.3Vaux 12 13 CLK GND 14 15 GND PMCGNT1# 16 17 PMCREQ1# +5V 18 19 +3.3V (VIO) AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C/BE3# 26 27 AD22 AD21 28 29 AD19 +5V 30 31 +3.
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Pin Assignments Table 5-3 PMC Slot 1 Connector (J11) Pin Assignments (continued) Pin Signal Signal Pin 61 AD00 +5V 62 63 GND REQ64# 64 Table 5-4 PMC Slot 1 Connector (J12) Pin Assignments Pin Signal Signal Pin 1 +12V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull-up +3.3V 12 13 RST# Pull-down 14 15 +3.3V Pull-down 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 +3.
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Pin Assignments Table 5-4 PMC Slot 1 Connector (J12) Pin Assignments (continued) Pin Signal Signal Pin 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 +3.3V 50 51 AD07 REQ1B# 52 53 +3.3V GNT1B# 54 55 Not Used GND 56 57 Not Used EREADY0 58 59 GND Not Used 60 61 ACK64# +3.
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Pin Assignments Table 5-5 PMC Slot 1 Connector (J13) Pin Assignments (continued) Pin Signal Signal Pin 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 +3.3V (VIO) AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 +3.
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Pin Assignments Table 5-6 PMC Slot 1 Connector (J14) Pin Assignments (continued) Pin Signal Signal Pin 13 PMC1_13 (P2-C7) PMC1_14 (P2-A7) 14 15 PMC1_15 (P2-C8) PMC1_16 (P2-A8) 16 17 PMC1_17 (P2-C9) PMC1_18 (P2-A9) 18 19 PMC1_19 (P2-C10) PMC1_20 (P2-A10) 20 21 PMC1PMC1_21 (P2-C11) PMC1_22 (P2-A11) 22 23 PMC1_23 (P2-C12) PMC1_24 (P2-A12) 24 25 PMC1_25 (P2-C13) PMC1_26 (P2-A13) 26 27 PMC1_27 (P2-C14) PMC1_28 (P2-A14) 28 29 PMC1_29 (P2-C15) PMC1_30 (P2-A15) 30 31 PMC1_3
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Pin Assignments Table 5-7 PMC Slot 2 Connector (J21) Pin Assignments Pin Signal Signal Pin 1 TCK -12V 2 3 GND INTC# 4 5 INTD# INTA# 6 7 PMCPRSNT1# +5V 8 9 INTB# PCI_RSVD 10 11 GND +3.3Vaux 12 13 CLK GND 14 15 GND PMCGNT1# 16 17 PMCREQ1# +5V 18 19 +3.3V (VIO) AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C/BE3# 26 27 AD22 AD21 28 29 AD19 +5V 30 31 +3.
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Pin Assignments Table 5-7 PMC Slot 2 Connector (J21) Pin Assignments (continued) Pin Signal Signal Pin 55 AD04 GND 56 57 +3.3V (VIO) AD03 58 59 AD02 AD01 60 61 AD00 +5V 62 63 GND REQ64# 64 Table 5-8 PMC Slot 2 Connector (J22) Pin Assignments Pin Signal Signal Pin 1 +12V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull-up +3.3V 12 13 RST# Pull-down 14 15 +3.
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Pin Assignments Table 5-8 PMC Slot 2 Connector (J22) Pin Assignments (continued) Pin Signal Signal Pin 39 PERR# GND 40 41 +3.3V SERR# 42 43 C/BE1# GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 +3.3V 50 51 AD07 REQ1B# 52 53 +3.3V GNT1B# 54 55 Not Used GND 56 57 Not Used EREADY1 58 59 GND Not Used 60 61 ACK64# +3.
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Pin Assignments Table 5-9 PMC Slot 2 Connector (J23) Pin Assignments (continued) Pin Signal Signal Pin 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 +3.3V (VIO) AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 +3.
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Pin Assignments 5.2.4 Serial Port Connectors (COM1/J41A, COM2—COM5/J2A-D) There is one front access asynchronous serial port interface (SP0) that is routed to the RJ-45 front-panel connector. There are four asynchronous serial port interfaces, SP1 — SP4, which are routed to the P2 connector. The pin assignments for these connectors are as follows: Table 5-10 COM Port Connector Pin Assignments Pin Signal 1 No connect 2 RTS 3 GND 4 TX 5 RX 6 GND 7 CTS 8 No connect 5.2.
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Pin Assignments Table 5-11 VMEbus P1 Connector Pin Assignments (continued) ROW Z ROW A ROW B ROW C ROW D 8 GND D07 BG2IN* D15 Reserved 8 9 Reserved GND BG2OUT* GND GAP_L 9 10 GND SYSCLK BG3IN* SYSFAIL* GA0_L 10 11 Reserved GND BG3OUT* BERR* GA1_L 11 12 GND DS1* BR0* SYSRESET* Reserved 12 13 Reserved DS0* BR1* LWORD* GA2_L 13 14 GND WRITE* BR2* AM5 Reserved 14 15 Reserved GND BR3* A23 GA3_L 15 16 GND DTACK* AM0 A22 Reserved 16 17 Reserved
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Pin Assignments 5.2.6 VMEbus P2 Connector The VME P2 connector is a 160-pin DIN. Row B of the P2 connector provides power to the MVME3100 and to the upper eight VMEbus address lines and additional 16 VMEbus data lines.
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Pin Assignments Table 5-12 VME P2 Connector Pinouts (continued) Pin P2-Z P2-A P2-B P2-C P2-D 23 SP3RTS PMC1_IO46 VD24 PMC1_IO45 E2-3- 24 GND PMC1_IO48 VD25 PMC1_IO47 E2-3+ 25 SP4RX PMC1_IO50 VD26 PMC1_IO49 GND 26 GND PMC1_IO52 VD27 PMC1_IO51 E2-2- 27 SP4TX PMC1_IO54 VD28 PMC1_IO53 E2-2+ 28 GND PMC1_IO56 VD29 PMC1_IO55 GND 29 SP4CTS PMC1_IO58 VD30 PMC1_IO57 E2-1- 30 GND PMC1_IO60 VD31 PMC1_IO59 E2-1+ 31 SP4RTS PMC1_IO62 GND PMC1_IO61 GND 32 GND P
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Pin Assignments Table 5-13 MVME721 Host I/O Connector (J10) Pin Assignments (continued) Pin Signal Signal Pin 17 No Connect GND 18 19 No Connect No Connect 20 21 +5V No Connect 22 23 No Connect No Connect 24 25 No Connect +3.3V 26 27 No Connect No Connect 28 29 GND No Connect 30 31 No Connect No Connect 32 33 No Connect GND 34 35 No Connect No Connect 36 37 +5V No Connect 38 39 No Connect No Connect 40 41 No Connect +3.
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Pin Assignments 5.2.8 Planar sATA Power Connector (J30) There is one 2mm pitch header installed as a planar header on the MVME3100 board to provide power to a serial ATA (sATA) drive mounted on the board or somewhere within the chassis. The pin assignments for this header are as follows: Table 5-14 Planar sATA Power Connector (J30) Pin Assignments Pin Signal 1 +5V 2 +5V 3 GND 4 GND 5.2.9 USB Connector (J27) There is one USB Type A connector located on the MVME3100 front panel.
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Pin Assignments 5.2.10 sATA Connectors (J28 and J29) The MVME3100 has two sATA connectors. J28 is an internal type sATA connector located on the planar and is intended to connect to a drive located on the board or somewhere inside the chassis. J29 is an external type sATA connected located on the front panel and is intended to connect to an external sATA drive.
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Pin Assignments Table 5-17 Boundary Scan Header (J24) Pin Assignments (continued) Pin Signal Signal Pin 5 TDI GND 6 7 TMS GND 8 9 TCK GND 10 11 NC GND (BSCANEN_L) 12 13 BSCAN_AW_L GND 14 Pin 12 must be grounded in the cable in order to enable boundary scan. 5.3.2 Processor COP Header (J25) There is one standard 16-pin header that provides access to the COP function.
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Chapter 6 Memory Maps 6.1 Memory Maps 6.1.1 Default Processor Memory Map The MPC8540 presents a default processor memory map following RESET negation. The following table shows the default memory map from the point of view of the processor. The e500 core only provides one default TLB entry to access boot code and it allows for accesses within the highest 4KB of memory.
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Memory Maps 6.1.2 MOTLoad’s Processor Memory Map MOTLoad’s processor memory map is given in the following table. Table 6-2 MOTLoad’s Processor Address Map Processor Address Start End Size Definition Notes 0000 0000 top_dram-1 dram_size (2GB max) System Memory (on-board DRAM) 8000 0000 DFFF FFFF 1.
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Memory Maps 6.1.4 System I/O Memory Map System resources including System Control and Status registers, external timers, and the QUART are mapped into a 16MB address range from the MVME3100 via the MPC8540 local bus controller (LBC).
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Memory Maps Table 6-3 System I/O Memory Map (continued) LBC Bank / Chip Select Address Definition Notes E201 5000 E201 FFFF Reserved E202 0000 External PLD Tick Timer Prescaler Register 4 2 E202 0010 External PLD Tick Timer 1 Control Register 4 2 E202 0014 External PLD Tick Timer 1 Compare Register 4 2 E202 0018 External PLD Tick Timer 1 Counter Register 4 2 E202 001C Reserved 4 2 E202 0020 External PLD Tick Timer 2 Control Register 4 2 E202 0024 External PLD Tick Timer 2 Com
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Memory Maps 6.1.5 System Status Register The MVME3100 board System Status register is a read-only register used to provide board status information. System Status Register — 0xE2000000 BIT 7 6 5 4 3 2 RSVD RSVD SAFE_START ABORT RSVD 0 0 X 0 0 FIELD OPER R RESET 0 1 0 BD_TYPE REG RSVD Table 6-4 System Status Register 0 0 BD_TYPE Board type. These bits indicate the board type.
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Memory Maps 6.1.6 System Control Register The MVME3100 board System Control register provides board control bits. Table 6-5 System Control Register REG System Control Register - 0xE2000001 BIT 7 6 5 4 3 2 1 0 0 0 TSTAT_MASK 0 EEPROM_WP RESET RSVD R/W RSVD OPER RSVD BD_RESET FIELD R R R R/W R/W 0 0 X 1 1 TSTAT_MASK: Thermostat mask. This bit masks the DS1621 temperature sensor thermostat output.
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Memory Maps 6.1.7 System Indicator Register The MVME3100 board provides a System Indicator register that may be read by the system software to determine the state of the on-board status indicator LEDs or written to by system software to illuminate the corresponding on-board LEDs.
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Memory Maps 6.1.8 Flash Control/Status Register The MVME3100 provides software-controlled bank write protect and map select functions as well as boot block select, bank write protect, and activity status for the Flash. Table 6-7 Flash Control/Status Register REG Flash Control/Status Register - 0xE2000003 BIT 7 6 5 4 3 2 1 0 RSVD RSVD RSVD MAP_SEL F_WP_SW F_WP_HW FBT_BLK_SEL FLASH_RDY FIELD OPER R R R R/W R/W R R R RESET 0 0 0 0 1 X X 1 FLASH_RDY: Flash ready.
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Memory Maps RSVD: Reserved for future implementation. 6.1.9 PCI Bus Status Registers The PCI Bus Status registers provide PCI bus configuration information for each of the PCI buses. Table 6-8 PCI Bus A Status Register PCI Bus A Status Register - 0xE2000004 BIT 7 6 5 4 3 2 0 RSVD RSVD RSVD RSVD PCI_A_64B PCIX_A FIELD 1 PCI_A_SPD REG OPER R R R R R R R R RESET 0 0 0 0 1 X 0 1 PCI_A_SPD PCI bus A speed. Indicates the frequency of PCI bus A.
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Memory Maps Table 6-9 PCI Bus B Status Register (continued) 3.3V_VIO 5.0V_VIO ERDY2 ERDY1 PCI_B_64B PCIX_B FIELD PCI Bus B Status Register - 0xE2000005 PCI_B_SPD REG OPER R R R R R R R R RESET X X X 0 1 X X X PCI_B_SPD: PCI bus B speed. Indicates the frequency of PCI bus B. 00: 33 MHz 01: 66 MHz 10: 100 MHz 11: 133 MHz PCIX_B: PCI-X bus B. A set condition indicates that bus B is operating in PCI-X mode. A cleared condition indicates PCI mode. PCI_B_64B: PCI bus B 64-bit.
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Memory Maps 3.3V_VIO: 3.3V VIO enabled. This bit set indicates that the PMC bus (PCI bus B) is configured to 3.3V VIO. Table 6-10 PCI Bus C Status Register PCI Bus C Status Register - 0xE2000006 BIT 7 6 5 4 3 2 0 RSVD RSVD RSVD RSVD PCI_C_64B PCIX_C FIELD 1 PCI_C_SPD REG OPER R R R R R R R R RESET X X X 0 1 X X X PCI_C_SPD: PCI bus C speed. Indicates the frequency of PCI bus C. 00: 33 MHz 01: 66 MHz 10: 100 MHz 11: 133 MHz PCIX_C: PCI-X bus C.
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Memory Maps 6.1.10 Interrupt Detect Register The MVME3100 provides an Interrupt Detect register that may be read by the system software to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt. Table 6-11 Interrupt Detect Register REG Interrupt Detect Register - 0xE2000007 BIT 7 6 5 4 3 2 1 0 RSVD RSVD RSVD RSVD RSVD FEC_PHY TSEC2_PHY TSEC1_PHY FIELD OPER R R R R R R R R RESET 1 1 1 0 0 0 0 0 TSEC1_PHY: TSEC1 PHY interrupt.
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Memory Maps Table 6-12 Presence Detect Register (continued) REG RSVD RSVD RSVD RSVD RSVD PEP PMC2P PMC1P FIELD Presence Detect Register - 0xE2000008 OPER R R R R R R R R RESET 0 0 0 0 0 X X X PMC1P: PMC module 1 present. If cleared, there is no PMC module installed in site 1. If set, the PMC module is installed. PMC2P: PMC module 2 present. If cleared, there is no PMC module installed in site 2. If set, the PMC module is installed. PEP: PMCspan present.
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Memory Maps 6.1.13 PLD Data Code Register The MVME3100 PLD provides a 32-bit register that contains the build date code of the timers/registers PLD. Table 6-14 PLD Data Code Register REG PLD Data Code Register - 0xE200000C BIT 31:24 23:16 15:8 7:0 FIELD yy mm dd vv OPER R/W RESET xxxx yy: Last two digits of the year mm: Month dd: Day vv: Version 6.1.
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Memory Maps 6.1.15 Test Register 2 The MVME3100 provides a second 32-bit test register that reads back the complement of the data in test register 1. Table 6-16 Test Register 2 REG Test Register 2 - 0xE2000014 BIT 31:0 FIELD TEST2 OPER R/W RESET FFFF TEST2: A read from this address returns the complement of the data pattern in test register 1. A write to this address writes the uncomplemented data to register TEST1. 6.1.
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Memory Maps Prescalar Adjust: The prescaler adjust value is determined by the following formula: Prescaler adjust = 256 - (CLKIN/CLKOUT) where CLKIN is the input clock source in MHz and CLKOUT is the desired output clock reference in MHz. 6.1.16.2 Control Registers The prescaler provides the clock required by each of the four timers. The tick timers require a 1 MHz clock input. The input clock to the prescaler is 25 MHz.
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Memory Maps INTS: Interrupt status. RSVD: Reserved for future implementation. 6.1.16.3 Compare Registers The tick timer counter is compared to the Compare register. When they are equal, the tick timer interrupt is asserted and the overflow counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared.
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Memory Maps 6.1.16.4 Counter Registers When enabled, the tick timer Counter register increments every microsecond. Software may read or write the counter at any time. Table 6-20 Tick Timer Counter Registers REG Tick Timer 1 Counter Register - 0xE202 0018 (32 bits) Tick Timer 2 Counter Register - 0xE202 0028 (32 bits) Tick Timer 3 Counter Register - 0xE202 0038 (32 bits) Tick Timer 4 Counter Register - 0xE202 0048 (32 bits BIT 31 FIELD Tick Timer Counter Value OPER R/W RESET 0 0 6.1.
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Chapter 7 Programming Details 7.1 Introduction This chapter includes additional programming information for the MVME3100 single-board computer.
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Programming Details 7.2 MPC8540 Reset Configuration The MVME3100 supports the power-on reset (POR) pin sampling method for MPC8540 reset configuration. The states of the various configuration pins on the MPC8540 are sampled when reset is de-asserted to determine the desired operating modes. The following table describes the configuration options and the corresponding default setting.
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Programming Details Table 7-1 MPC8540 Power-on Reset Configuration Settings (continued) MPC8540 Signal Select Option Default Setting TSEC1_ TXD7 Resistor 0 TSEC1_ TXD [6:4] TSEC2_ TXD7 Resistors Resistor 111 0 Description State of Bit vs Function 1 TSEC1 Protocol Configuration 0 TSEC1 controller uses GMII protocol (RGMII if TSEC1 configured in reduced mode) 1 TSEC1 controller uses TBI protocol (RTBI if TSEC1 configured in reduced mode) 000 PCI/PCI-X 001 DDR SDRAM 011 RapidIO 101 L
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Programming Details Table 7-1 MPC8540 Power-on Reset Configuration Settings (continued) MPC8540 Signal Select Option Default Setting TSEC2_ TXD [6:5] Resistors 11 Description State of Bit vs Function 1 Local Bus Output Hold Configuration 00 0 added buffer delays (0 added buffer delays for LALE) 01 3 added buffer delays (1 added buffer delay for LALE) 10 2 added buffer delays (1 added buffer delay for LALE) 11 1 added buffer delay (0 added buffer delays for LALE) TSEC2_ TXD [2:4] Fixed 00
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Programming Details Table 7-1 MPC8540 Power-on Reset Configuration Settings (continued) MPC8540 Signal Select Option Default Setting LWE [0:1] _L 4 Resistors 11 11 LWE [2:3] _L LALE, LGPL2 LGPL0, LGPL1 Resistors Resistor Fixed 11 01 11 Description State of Bit vs Function 1 PCI Output Hold Configuration 00 1 added buffer delay 01 0 added buffer delays 10 3 added buffer delays 11 2 added buffer delays5 00 3 added buffer delays 01 2 added buffer delays 10 1 added buffer delay
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Programming Details Table 7-1 MPC8540 Power-on Reset Configuration Settings (continued) MPC8540 Signal Select Option Default Setting LGPL3, LGPL5 Fixed 11 Description State of Bit vs Function 1 Boot Sequencer Configuration 00 Reserved 01 Boot sequencer enabled with normal I2C address mode 10 Boot sequencer enabled with extended I2C address mode 11 Boot sequencer disabled LAD [28:31] Resistor 7 XX General-Purpose POR Configuration XX General-purpose POR configuration vector to be place
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Programming Details 7. Local bus LAD[0:31] is sampled during POR, but only LAD[28:31] are configurable by resistor option. Software can use this value to inform the firmware or operating system about initial board configuration. 8. ECC signals from memory devices must be disconnected. 7.3 MPC8540 Interrupt Controller The MVME3100 uses the MPC8540 integrated programmable interrupt controller (PIC) to manage locally generated interrupts.
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Programming Details 7.4 Local Bus Controller Chip Select Assignments The following table shows local bus controller (LBC) bank and chip select assignments for the MVME3100 board.
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Programming Details Table 7-4 I2C Bus Device Addressing (continued) I2C Bus Address Device Address A2 A1 A0 (binary) Size (bytes) Device Function Notes $A0 000 256 x 8 DDR memory SPD (SODIMM module banks 1 and 2 corresponding to MPC8540 memory controller chip selects 0 and 1) 1 $A2 001 $A4 010 65,536 x 8 User configuration 2 $A6 011 65,536 x 8 User configuration 2 $A8 100 8192 x 8 VPD (on-board system configuration) 2 $AA 101 8192 x 8 RTM VPD (off-board configuration) 2, 3 $
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Programming Details 7.7 VPD EEPROM The MVME3100 board provides an 8KB dual address serial EEPROM containing vital product data (VPD) configuration information specific to the MVME3100. Typical information that may be present in the EEPROM may include: manufacturer, board revision, build version, date of assembly, memory present, options present, L2 cache information, etc. The VPD EEPROM is hardwired to have a device ID as shown in Table 7-4 on page 130.
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Programming Details 7.10 Flash Memory The MVME3100 is designed to provide one or two physical banks of soldered-on Flash memory. Each bank may be populated with two AMD Spansion MirrorBit 3.0V devices configured to operate in 16-bit mode to form a 32-bit Flash bank. The Flash bank connected to LBC Chip Select 0 is the boot bank and is always populated. The second Flash bank connected to LBC Chip Select 1 may or may not be populated depending on Flash size requirements and available Flash devices.
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Programming Details switch is ON, block B is mapped to the highest address as shown below. The MAP_SEL bit in the Flash Control/Status register can override the switch and restore the memory map to the normal configuration with block A selected. Upon RESET, this mapping reverts to the switch selection. 7.11 PCI IDSEL Definition Each PCI device has an associated address line connected via a resistor to its IDSEL pin for configuration space accesses.
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Programming Details Table 7-7 IDSEL and Interrupt Mapping for PCI Devices (continued) Device Number Field PCI Bus C (PCI6520-2) PCI Expansion (21150) AD Line for IDSEL PCI Device or Slot Device/Slot INT to MPC8540 Ext IRQ INTA# INTB# INTC# IRQ4 IRQ5 IRQ6 INTD# 0b0_0000 16 uPD740101 USB 0b0_0100 20 21150 on PMCSpan 0b0_0010 18 PMCSpan Slot 1 IRQ6 IRQ7 IRQ4 IRQ5 0b0_0011 19 PMCSpan Slot 2 IRQ7 IRQ4 IRQ5 IRQ6 0b0_0100 20 PMCSpan Slot 3 IRQ4 IRQ5 IRQ6 IRQ7 0b0_0101 21
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Programming Details 7.12 PCI Arbitration Assignments The integrated PCI/X arbiters internal to the MPC8540 and the PCI6520 bridges provide PCI arbitration for the MVME3100. The MPC8540 provides arbitration support for itself and the four PCI-X devices on PCI bus A. The PCI6520 secondary PCI/X interface arbiters support external bus masters in addition to the PCI6520.
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Programming Details the clocks required on the MVME3100 along with their frequency and source. The clock tree A frequencies on bus A have a default configuration of 66 MHz. The 33/66/100 MHz clocks are dynamically configured at reset depending on the state of the PCIXCAP and M66EN pins on bus B. The PCI clock trees A, B, and C are not required to be synchronized with each other.
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Programming Details Table 7-10 Clock Assignments (continued) Device Clock Signal(s) Frequency (MHz) Control and Timers PLD CLK25_33V_PLD 25 CLK_LBC QUART Clock Tree Source Qty VIO Oscillator/ Buffer 1 3.3V CCB_CLK/8 (333 MHz/8) MPC8540 1 3.3V CLK_UART 1.8432 Oscillator 1 3.3V sATA CLK25 25 Oscillator 1 3.3V USB CLK48 48 Oscillator 1 3.3V RTC CLK32 32.768 kHz Crystal 1 3.3V 7.
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Appendix A A Specifications A.1 Power Requirements In its standard configuration, the MVME3100 requires +5 V for operation. On-board converters supply the processor core voltage, +3.3 V, +1.8 V, and +2.5 V. For any installed PMC card that requires +12 V or -12 V, these voltages must be supplied by the chassis. Table A-1 provides an estimate of the typical and maximum current required from each of the input supply voltages.
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Specifications Product Damage A.3 z High humidity and condensation on surfaces cause short circuits. z Do not operate the product outside the specified environmental limits. Make sure the product is completely dry and there is no moisture on any surface before applying power. Thermally Significant Components The following table summarizes components that exhibit significant temperature rises. These are the components that should be monitored in order to assess thermal performance.
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Specifications Primary Side Components U1012 XU1 U1051 U5000 U1052 U21 U1010 Figure A-1 MVME3100 Single Board Computer Installation and Use (6806800M28C) 141
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Specifications The preferred measurement location for a component may be junction, case, or ambient as specified in the table. Junction temperature refers to the temperature measured by an on-chip thermal device. Case temperature refers to the temperature at the top, center surface of the component. Air temperature refers to the ambient temperature near the component.
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Appendix B B Related Documentation B.1 Emerson Network Power - Embedded Computing Documents The Emerson Network Power - Embedded Computing publications listed below are referenced in this manual. You can obtain electronic copies of Emerson Network Power - Embedded Computing publications by contacting your local Emerson sales office. For documentation of final released (GA) products, you can also visit the following website: http://www.emersonnetworkpowerembeddedcomputing.
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Related Documentation Table B-2 Manufacturers’ Documents (continued) Document Title and Source Publication Number Tsi148 PCI/X to VME Bus Bridge User Manual 80A3020_MA001_02 Tundra Semiconductor Corporation 603 March Road Ottawa, Ontario, Canada K2K 2M5 Web Site: www.tundra.com BCM5421S 10/100/1000BASE-T Gigabit Transceiver BCM5421 Broadcom Corporation Web Site: www.broadcom.com BCM5221S 10/100BASE-Tx Single-Channel Signi-PHY Transceiver BCM5221 Broadcom Corporation Web Site: www.broadcom.
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Related Documentation Table B-2 Manufacturers’ Documents (continued) Document Title and Source Publication Number 2-Wire Serial EEPROM AT24C512 Atmel Corporation San Jose, CA Web Site: www.atmel.com/atmel/support Maxim DS1621 Digital Thermometer and Thermostat DS1621 Maxim Integrated Products Web Site: www.maxim-ic.com Maxim DS1375 Serial Real-Time Clock Rev: 121203 Maxim Integrated Products Web Site: www.maxim-ic.com TSOP Type I Shielded Metal Cover SMT Yamaichi Electronics USA Web Site: www.yeu.
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Related Documentation Table B-3 Related Specifications (continued) Document Title and Source Publication Number IEEE http://www.ieee.org IEEE - Common Mezzanine Card Specification (CMC) Institute of Electrical and Electronics Engineers, Inc. P1386 Draft 2.0 IEEE - PCI Mezzanine Card Specification (PMC) P1386.1 Draft 2.0 Institute of Electrical and Electronics Engineers, Inc. USB http://www.usb.org/developers/docs Universal Serial Bus Specification 146 Revision 2.
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Related Documentation MVME3100 Single Board Computer Installation and Use (6806800M28C) 147
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Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
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Safety Notes This is a Class A product based on the standard of the Voluntary Control Council for Interference by Information Technology Interference (VCCI). If this equipment is used in a domestic environment, radio disturbance may arise. When such trouble occurs, the user may be required to take corrective actions. The blade generates and uses radio frequency energy and, if not installed properly and used in accordance with this guide, may cause harmful interference to radio communications.
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Safety Notes Operation Product Damage High humidity and condensation on surfaces cause short circuits. Do not operate the product outside the specified environmental limits. Make sure the product is completely dry and there is no moisture on any surface before applying power. Environment Environmental Damage Improperly disposing of used products may harm the environment. Always dispose of used products according to your country’s legislation and manufacturer’s instructions.
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Safety Notes MVME3100 Single Board Computer Installation and Use (6806800M28C) 151
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Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind.
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Sicherheitshinweise EMV Das Blade wurde in einem Emerson Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Blades in Gewerbe- sowie Industriegebieten gewährleisten. Das Blade arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung.
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Sicherheitshinweise Schaltereinstellungen Fehlfunktion des Produktes Schalter, die mit 'Reserved' gekennzeichnet sind, können mit produktionsrelevanten Funktionen belegt sein. Das Ändern dieser Schalter kann im normalen Betrieb Störungen auslösen. Verstellen Sie nur solche Schalter, die nicht mit 'Reserved' gekennzeichnet sind. Betrieb Beschädigung des Blades Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Blades können zu Kurzschlüssen führen.
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HOW TO REACH LITERATURE AND TECHNICAL SUPPORT: Tempe, Arizona, USA 1 800 759 1107 1 602 438 5720 Munich, Germany +49 89 9608 0 For literature, training, and technical assistance and support programs, visit www.emersonnetworkpowerembeddedcomputing.com Emerson Network Power. The global leader in enabling Business-Critical Continuity™ AC Power Systems Connectivity DC Power Systems Embedded Computing Embedded Power Integrated Cabinet Solutions www.emersonnetworkpowerembeddedcomputing.