Instruction manual

3-20 / Service ControlWaveLP
4. When you have finished with Ethernet Diagnostic Loop-back testing, be sure to return the
hardware to its normal operating configuration, i.e., disconnect the loop-back cable or jack-
plug and reconnect the Ethernet cable to both the ControlWaveLP port in question and
the Ethernet Hub.
3.4.1.3.2 Ethernet Port Return Hardware Address Test Procedure
1. Set the ‘Number of Passes’ to “5” and type "1" for the ‘Ethernet Port to Test.’
2. Click on the "RUN Return hardware address” test button. The test will proceed and if
successful the hardware address will be displayed. The hardware address will appear as
00-10-41-XX-XX-XX. The prefix 00-10-41 appears for all BBI Ethernet Comm. ports. The
remainder of the hardware address is unique for each board manufactured and is stored in
memory. If the error message “Error Information Returned” is displayed instead of the
hardware address, and the unit has been programmed with a proper hardware address,
the CPU Module should be replaced.
3.5 CORE UPDUMP
In some cases a copy of the contents of SRAM can be uploaded to a PC for evaluation by
Bristol, Inc. engineers. This upload is referred to as a ‘Core Updump.’ A Core Updump may
be required if the ControlWaveLP Process Automation Controller repeatedly enters a
‘Watchdog State’ thus ill effecting system operation. A Watchdog State is entered when the
system crashes, i.e., a CPU timeout occurs due to improper software operation, a firmware
glitch, etc. In some cases the Watchdog State may reoccur but may not be logically
reproduced.
‘Crash Blocks’ (a function of firmware provided for watchdog troubleshooting) are stored in
CPU RAM. The user can view and save the ‘Crash Blocks’ by viewing the Crash Block
Statistic Web Page (see Chapter 4 of the Open BSI Technician’s Toolkit - D5087). Crash
Block files should be forwarded to Bristol for evaluation. If additional information is
required to evaluate the condition, a Core Updump may be requested by Bristol. Once the
file generated by the Core Updump has been forwarded to Bristol, it will be evaluated and
the results will be provided to the user.
Follow the five steps below to perform a Core Updump.
1. Disable the Watchdog Timer by setting CPU Switch SW4-1 to the OFF position.
2. Wait for the error condition (typically a binary value of FF on the Status LEDs).
3. Connect the ControlWave’s Comm Port 1 to a PC using a Null Modem Cable (see
Figure 2-5).
4. Set CPU Board Switch SW4-4 to the OFF position to enable the Core Updump feature.
Start the PC’s HyperTerminal Program (at 115.2kbaud) and generate a receive using the X-
Modem protocol. Save the resulting Core Updump in a file to be forwarded to Bristol, Inc.
for evaluation.