Instruction manual

ControlWaveLP Introduction / 1-11
CPU Bd. Momentary Switch SW3 - CPU Reset
SW3 is a momentary switch that is used to reset the ControlWaveLP if it goes into a
watchdog condition.
CPU Bd. DIP Switch SW4
Eight-bit DIP Switch SW4 is provided for user configuration settings (see Table 1-8).
Table 1-8 - Assignment of CPU Bd. Switch SW4 - User Configurations
SW# Function Setting
SW4-1 Watchdog Enable
ON = Watchdog circuit is enabled
OFF = Watchdog circuit is disabled
SW4-2
Lock/Unlock
Soft Switches
ON = Write to Soft Switches or FLASH files
OFF = Soft Switches, configurations and FLASH files are locked
SW4-3
Use/Ignore
Soft Switches
ON = Use Soft Switches (configured in FLASH)
OFF = Ignore Soft Switch Configuration and use factory defaults
SW4-4
Normal Run or
Core Updump
ON = Normal Run Mode
OFF = Causes the system to start a Core Updump
SW4-5 SRAM Control
ON = Retain values in SRAM during restarts
OFF = Force system to reinitialize SRAM
SW4-6
System Firmware
Load Control *
ON = Enable remote download of System Firmware
OFF = Disable remote download of System Firmware
SW4-7 Not Used Leave ‘ON’
SW4-8 Enable WINDIAG
ON = Don’t allow WINDIAG to run test
OFF = Disable boot project and allow WINDIAG to run test
* = Boot PROM version 4.7 or higher and System PROM version 4.7 or higher
1.3.1.4 CPU Board Batteries
The CPU Board has a coin cell socket (S2) for providing backup of the real-time clock,
CMOS RAM and the on-board System SRAM. The cell used is a 3V, 1200 mA-hr lithium
coin cell. The battery, R400 and system SRAM are specified to allow a battery backup
period of 4000 hours minimum.
The R400EX will typically draw between 6uA and 7uA when the system is not being
powered externally. The system SRAM is specified to have a standby current draw of 20uA
maximum for each part.
A supervisory circuit is used to switch to battery power when VCC falls below VCC-10%.
1.3.2 Power Supply/Sequencer Board
The Power Supply/Sequencer Board (PSSB) measures 5.5” x 4” and plugs into the bottom of
the FMI/OB Board [via 20-pin connectors (PSSB - J1) (FMI/OB - P9)]. There are two non-
pluggable terminal blocks for input power and the watchdog relay.
PSSBs contain a power supply that generates isolated DC supplies (+5V (VCC), +12V and -
12V) for the CPU, the logic element of the FMI/OB subsystem and optional PC/104 cards.
Also contained on the PSSB is the sequencer circuit which monitors the incoming power as
well as the isolated supplies. Master Clear (MC) and Power Fail Indication (PFIN) are
generated by the sequencer circuit when incoming power or the supply voltages fall below
specified limits. The sequencer circuit works in conjunction with an ADC circuit that
monitors the incoming voltage level. Additionally, the sequencer circuit controls a watchdog
relay.