Instruction manual

1-8/Introduction ControlWaveLP
CPU Bd. Connectors J10 & J11 - PC/104 Bus (CPU Bd. To FMI/OB Bd.)
Connections to the ISA bus are available on the PC/104 bus via CPU/FMI/OB Interface
Connectors J10 and J11 (J10 of CPU mates with P7 of FMI/OB and J11 of CPU mates with
P10 of FMI/OB) (see Table 4-4). ISA bus signals are provided by the RadiSys R400EX
system controller. During non-ISA bus cycles, the R400EX places the ISA bus into a quiet
mode to reduce overall power consumption. The external interface to PC/104 cards is level
shifted to a 5V bus through a set of buffers and transceivers and is capable of driving up to
10 PC/104 cards.
The OSC signal on the PC/104 bus is a 6MHz clock signal that does not stop or change
frequency when the CPU clock is stopped or throttled. The BCLK signal on the PC/104 bus
is synchronous to the CPU clock, and is the clock to which the PC/104 interface signal
timing is referenced.
CPU Bd. PLD JTAG Connectors J12 & J24
Programmable Logic Device (PLD) Joint Technical Assessment Group (JTAG) 10-pin
headers J24 and J12 are provided for programming and ATE testing of on-board PLDs.
Connector J24 is associated with the Local Configuration PLD while connector J12 func-
tions in conjunction with the ISA PLD.
CPU Bd. CPU JTAG Connector J13
CPU Joint Technical Assessment Group (JTAG) 10-pin header J13 is provided for ATE
testing of the CPU logic.
CPU Bd. Manufacturing Test Power Connector J14
10-pin connector J14 provides +5V, +12V, -12V and Ground (GND) points that are used for
testing during manufacturing or diagnostic testing.
CPU Bd. Connector J15 - Port 80 Diagnostics
14-pin connector J15 on the CPU Board allows a diagnostic board to be plugged in for
testing. This connector has the necessary signals to implement a Port-80 display. The Port-
80 display is intended for displaying POST codes during system boot and test application.
The diagnostic board that plugs into this connector contains (functionally) a pair of data
latches and decoders that drive a pair of 7-segment LED displays. This diagnostic board is
factory utilized during board manufacturing/repair.
CPU Bd. Connector J19 - Ethernet Port
8-pin RJ-45 connector J19 provides a 10base-T Ethernet Port. The Ethernet interface is
implemented by an AMD Am79C961A Pcnet - ISA controller.
1.3.1.2 CPU Board User Configurable Jumpers
The CPU Board contains ten (10) user configurable Jumpers that function as follows:
Table 1-2 - CPU Board Default Jumper Settings
JUMPER Open Installed
JP1A - Expansion Card Battery Enable
⌦
JP1B - On-board SRAM & RTC Battery Enable
⌦
JP1C - OSCOFF Enable Jumper
⌦
JP2 - IRQ15 Source Select
⌦ (pins 1 & 2)