User manual

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2.3.2 CN2 90pin DIP Interface (left row)
Pins
Definitions
Descriptions
1
G_NWE
GPMC Write Enable
2
G_NOE
GPMC Read Enable
3
G_NCS7/GPT8/G_DIR
GPMC Chip Select bit 7PWM / event
for GP timer 8GPMC / IO direction
control for use with external
transceivers
4
G_NCS4/DMAREQ1
GPMC Chip Select bit 7PWM /DMA
request 1
5
G_NCS6/DMAREQ3
GPMC Chip Select bit 7PWM / DMA
request 3
6
G_NCS3DMAREQ0
GPMC Chip Select bit 7External
DMA request 0
7
GND1
GND
8
G_WAIT0
External indication of wait
9
G_NBE0 / G_CLE
Lower Byte Enable. Also used for
Command Latch Enable
10
G_ALE
Address Latch Enable
11
G_NBE1
Upper Byte Enable
12
HDQ_SIO
Bidirectional HDQ 1-Wire control
and data
13
MMC1_D0
MMC/SD Card Data bit 0
14
MMC1_D1
MMC/SD Card Data bit 1
15
MMC1_D2
MMC/SD Card Data bit 2
16
MMC1_D6/IO128
MMC/SD Card Data bit 6
17
MMC1_D5/IO127
MMC/SD Card Data bit 5
18
MMC1_D4/IO126
MMC/SD Card Data bit 4
19
MMC1_D7/IO129
MMC/SD Card Data bit 7