User`s guide

LPC3250 Developer’s Kit - User’s Guide

Page 15

EMC_BLS2

EMC_BLS3

EMC_CKE1

EMC_CLKIN

EMC_DQM2

EMC_DQM3

EMC_DYCS1_N

No. These signals are not used and not

available.

KEY_COL0 / ENET_TX_CLK

KEY_ROW0 / ENET_TX_ER

KEY_ROW1 / ENET_TXD2

KEY_ROW2 / ENET_TXD3

No. These signals are not used and not

available.

Note that three (of four) signals can become

available if 0 ohm resistors are mounted:

 KEYROW0, mount R93

 KEYROW1, mount R94

 KEYCOL0, mount R91

JTAG signals

Yes

RESET_N

RESOUT_N

Yes

Note pull-up resistor on RESET_IN and

internal open-drain driving of RESET_IN

RTCX_IN

RTCX_OUT

SYSX_IN

SYSX_OUT

No, directly connected to on-board crystals

All VDD and VSS pins

No, not directly accessible, but ground is

available and 3.15-3.3V input voltage

PLL397_LOOP

No, internal on-board connection to signal.

The QVGA Base Board illustrates how to typically connect external interfaces (like USB, external

memory devices, etc) to the LPC3250 OEM Board. Study this schematic (also found in this document)

for details.

3.3 LPC3250 OEM Board Mechanical Dimensions and Connector

Figure 1 below contains a drawing of the board that includes mechanical measures. See SODIMM-200

standard for exact measures. 1.8V keying is used (SODIMM-200 boards are either 1.8V or 2.5V

keyed).