User`s guide

LPC3250 Developer’s Kit - User’s Guide
Page 11
Copyright 2011 © Embedded Artists AB
3.1.3.1 DDR SDRAM
A 512 MBit (64 MByte) Mobile DDR SDRAM is used (MT46H32M16LF from Micron). The chip is
powered by 1.8V and is organized as 32Mbit x16, i.e. it has 16-bit databus width. The chip is
connected to EMC_DYCS0_N (memory bank #0 for dynamic RAM) at address range 0x8000 0000 –
0x9FFF FFFF.
Note that memory bank #1 for dynamic RAM is not available (i.e., signal EMC_DYCS1_N is not used).
3.1.3.2 NAND Flash
A 1 Gbit (128 MByte) NAND flash is used (K9F1G08U0A-P from Samsung). The chip is powered by
3.3V and has 8-bit databus width. The NAND flash builds on a single-level cell (SLC) technology and
has a page size of 2112 bytes (2,048 + 64 bytes). Note that the chip is not directly accessible via the
memory bus. Instead, all accesses must be done via the on-chip NAND flash controller of the
LPC3250.
3.1.3.3 Buffers to External Interface
The LPC3250 memory interface is available on the expansion connector. The data bus width is 16-bits
on the external interface. The relevant signals are buffered. The following four static memory regions
are available for external access:
 External static bank #0 (0xE000 0000 – 0xE0FF FFFF)
16-bit databus width and 16MByte in size.
 External static bank #1 (0xE100 0000 – 0xE1FF FFFF)
16-bit databus width and 16MByte in size.
 External static bank #2 (0xE200 0000 – 0xE2FF FFFF)
16-bit databus width and 16MByte in size.
 External static bank #3 (0xE300 0000 – 0xE3FF FFFF)
16-bit databus width and 16MByte in size.
By default (R44 = 0 ohm, R43 not mounted), signal N_ABUF_EN is pulled low and the two buffers for
address and control signals (U13 and U14) are enabled and act as output (from the LPC3250 OEM
Board).
The buffered version of the LPC3250 signal OE controls the direction of the data bus buffer (U15).
During read operations the buffer acts as an input and during write operations it acts as an output. The
data bus buffer is controlled by the signals BLS0 and BLS1, each controlling lower and upper bytes of
the 16-bit databus. These signals are active when accessing the external static memory regions.
The buffers are dual voltage buffers and act as level translators between the internal 1.8V signal levels
and the external levels. Connect the external bus voltage to VDD_EXT. See the datasheet of
74AVCA164245 for exact details about voltage range. Normally 3.3V powering is used on the external
side.
3.1.4 Schematic Page 5: Digital and Analog IO
Page 5 of the schematic contains all digital and analog signals plus three LEDs controlled by signals
P2.10 - P2.12.
3.1.5 Schematic Page 6: Ethernet Interface
An external PHY (DP83848 from National Semiconductor) implements a 100/10Mbps Ethernet
interface. The external PHY is connected to the Ethernet MAC on the LPC3250 via the RMII interface.
3.1.6 Schematic Page 7: USB Interface
There is a USB 2.0 (OTG, Host, Device) interface on the LPC3250. An external PHY (ISP1301) is
needed for the cpu.