User`s guide

LPC3250 Developer’s Kit v2 - User’s Guide

Page 11

3 LPC3250 OEM Board Design

Please read the LPC3250 OEM Board datasheet and associated schematic for information about the

board. Some additional information about the LPC3250 OEM Board is presented below.

3.1 LPC3250 OEM Board Schematics

3.1.1 Schematic Page 2: Crystals

The microprocessor crystal frequency is 13.0000 MHz, which is the recommended frequency from

NXP. An internal PLL can create many other frequencies from this, like 208 MHz and 266 MHz.

The LPC3250 has an internal real-time clock (RTC) block that can be used to provide real-time and

alarm function. A 32.768 kHz crystal gives the base frequency for the RTC. The RTC block can be

powered via a separate supply (for example from a battery or high-capacity capacitor). The 32.768 kHz

can also be used as main oscillator via a PLL: 32.768 kHz x 397 = 13.009 MHz.

Note that the clocking structure is different from the LPC1xxx/2xxx family. It is a more complex

structure but also much more versatile and flexible. There is no shortcut but to read the

LPC3250 User’s Manual in detail to understand the options and settings.

3.1.2 Schematic Page 2: Booting

The LPC3250 starts executing from an on-chip ROM, containing the bootloader. Note that the

LPC3250 does not contain any on-chip FLASH memory. Program code must be loaded from an

external source into the on-chip SRAM.

The default boot is from an external memory (see LPC3250 User’s Manual for details). Program code

is typically stored in NAND or SPI-NOR flash.

By pulling pin GPI_01/SERVICE_N low, UART boot mode is activated. This is a method for

downloading code from the PC, for example for programming the bootloader for the first time. Note that

pin GPI_01/SERVICE_N can be pulled low by pressing SW6-key on the OEM Base Board.

3.1.3 Schematic Page 2: SPI NOR FLASH

There is a 32Mbit (4 MByte) NOR flash connected to the SPI bus. Embedded Artists can choose to

mount, either S25FL032P from Spansion, AT45DB321 from Atmel, or other, on the board depending

on component availability at the time of production. Mounted chips will be supported by the LPC3250

bootloader. However, commands used to program the memory differ. Chip id should always be read

out to determine exact type mounted.

3.1.4 Schematic Page 2: Reset Generation

The reset generation is handled by a standard voltage supervisor chip, CAT811R from Catalyst

Semiconductor. The reset signal will be held active (i.e., low) until the supply voltages, +3.3V, is within

margins (above 2.63V). The reset duration is typically 200 mS (consult the CAT811R datasheet for

exact details). The output reset signal is push/pull output that is converted to an open-collector / open-

drain output via the 74LVC1G125 buffer. An external reset source can pull the reset signal low (with an

open-collector/open-drain output). The RESET_N input on the LPC3250 has a 1.2V voltage range

(voltage domain: VDD_RTC). A 74LVC1G125 buffer makes sure this voltage range is not exceeded by

the external signal RESET_IN (which has 3.3V range).

3.1.5 Schematic Page 2: I2C E2PROM

There is a 256 kbit E2PROM accessible via the I2C interface (I2C1). The LPC3250 has two on-chip

I2C communication channels (I2C1 and I2C2). More peripheral units are easily connected to the two-

wire I2C bus, just as long as the addresses do not collide. The address of the 256kbit E2PROM is

0xA0, which is also indicated in the schematic.