Specifications

Chapter 3 – Input/Output Interfaces
88 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
mux
Event Register
Event Register
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
System Clock
Divide Chain
READ
TIMER/
COUNTER
FLAG AND
EVENT
REGISTER
CLEAR FLAG
END OF
io_in()
START OF
io_in()
STOP TIMER
COUNTER
START TIMER
COUNTER
TIME
Reference Figure 3.40
Optional Pull-Up Resistors
Timer/Counter 2
Timer/Counter 1
IO11
INPUT
t
fin
t
ret
Symbol Description Typ @ 10MHz
t
fin
Function call to input sample 86 µs
t
ret
Return from function 52/22 µs*
*If the measurement is new, t
ret
= 52µs. If a new time is not being returned, t
ret
= 22µs.
Figure 3.45 Period Input Latency Values
This is an edge-sensitive function. The clock driving the internal counter in the PL Smart Transceiver is free running.
The detection of active input edges stops and resets the counter each time.
The actual active edge of the input depends on whether or not the invert option was used in the declaration of the
function block. The default is the negative edge.