Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 87
Ontime Input
A timer/counter can be configured to measure the time for which its input is asserted. Table 3.8 shows the resolution and
maximum times for different I/O clock selections. Assertion can be defined as either logic high or logic low. This object
can be used as a simple analog-to-digital converter with a voltage-to-time circuit, or for measuring velocity by timing
motion past a position sensor (see Figures 3.40 and 3.44).
mux
Event Register
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
System Clock
Divide Chain
Optional Pull-Up Resistors
Reference Figure 3.40
Event Register
Timer/Counter 2
Timer/Counter 1
IO11
Symbol Description Typ @ 10MHz
t
fin
Function call to input sample 86 µs
t
ret
Return from function 52/22 µs*
*If the measurement is new, t
ret
= 52µs. If a new time is not being returned, t
ret
= 22µs.
Figure 3.44 Ontime Latency Values
This is a level-sensitive function. The active level of the input signal gates the clock driving the internal counter in the
PL Smart Transceiver.
The actual active level of the input depends on whether or not the invert option was used in the declaration of the
function block. The default is the high level.
Period Input
A timer/counter can be configured to measure the period from one rising or falling edge to the next corresponding edge
on the input. Table 3.8 shows the resolution and maximum time measured for various clock selections. This object is
useful for instantaneous frequency or tachometer applications. Analog-to-digital conversion can be implemented using a
voltage-to-frequency converter with this object (see Figure 3.45).