Specifications

Chapter 3 – Input/Output Interfaces
80 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
.
Param Description Min Typ Max Units
Tck Clock cycle (user specified)
Tsc Select low to Clock transition 4.8
μs
Tdoc Data out to Clock (1st bit of invert mode) 0.5*Tck ns
Tcdo Clock to data out 5 ns
Tdis Data in setup 10 ns
Tdih Data in hold 10 ns
Figure 3.38 SPI Master Mode Timing
IO0
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO11
SPI Master
IO0
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO11
SPI Master (Neurowire
pin mode)
Clock
MISO
MOSI
Clock
Data Out
Data In
Tcdo
Clock
(invert for
clockedge+
or
invert=true)
Data Out
Data In
Select
Tdis
Tdih
Tsc
Tdoc
Tck