Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 77
coexist with other slave mode devices on a 3 wire bus. A logic one level on the select line disables the output drivers of
the output pins and puts them in a high impedance state.
If the PL Smart Transceiver is the only slave device on the SPI bus and the master device does not drive the Slave
Select (SS~) signal, then either
Pin IO7 should be declared as an input pin and externally grounded.
OR
Pin IO7 must be declared in the following order:
IO_7 output bit io_p7_out = 1; // initialize to '1'
IO_7 input bit io_p7_in;
As long as the IO7 output bit is initialized to a 1 and the SS~ is disabled, IO7 can be used as an input. Note that SS~
should be used whenever possible to ensure proper synchronization and recovery in the event of framing errors from the
master device.
The bit rates supported by the SPI port are summarized in Tables 3.6 and 3.7
Table 3.6 Master mode
Clock 10MHz 6.5536MHz
7 19.531kbps 12.8kbps
6 39.063kbps 25.6kbps
5 78.125kbps 51.2kbps See Note
4 156.250kbps 102.4kbps See Note
3 312.500kbps 204.8kbps See Note
2 625.000kbps 409.6kbps See Note
1 1250.000kbps 819.2kbps See Note
0 2500.000kbps 1638.4kbps See Note
Note: For Clock 5 and higher bit rates, the bit rate shown is the peak rate. The data is burst out in pairs of bytes and the
overall average data rate is limited to approximately 40kbps and 25kbps for 10MHz and 6.5536MHz input clocks,
respectfully.
Table 3.7 Slave mode
10MHz 6.5536MHz
Max burst rate 1250kbps 819.2kbps
Max burst size 2 bytes 2 bytes
Min burst spacing 400us 640us
From start of one burst
to next.
Max sustained data
rate
40kbps 25kbps
Sustained reception in slave mode at maximum bit rate can starve the application processor and cause overruns and
presents a possible risk of watchdog timeout. Care must be given to allow the PL Smart Transceiver to process received
bytes in a timely manner. Master mode has no such restriction because the PL Smart Transceiver regulates the data
transfer.
The clockedge and invert keywords are used to determine the point at which data is sampled and the idle level of
the clock signal. The clock signal is idle at the logic 1 level. The invert keyword could be used to change the idle
state to correspond to a logic 0 level. Common SPI implementations use the terms clock phase (CPHA) and clock