Specifications

Chapter 3 – Input/Output Interfaces
76 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
are also supported for full-duplex transfers. No errors are introduced (other than inter-byte spacing of transmitted data)
under these conditions.
For 6.5536MHz operation, the bit rates are limited to a maximum of 19200 bits per second for both half and full-duplex
transfers.
The frame format is one start bit, eight data bits and one or two stop bits. Up to 255 output bytes and 255 input bytes can
be transferred at a time. If an input stop bit has the wrong polarity, the interface will attempt to recover and re-
synchronize. However, a framing error will be flagged in the status register. If necessary, the application code can use
other bit I/O pins for flow-control handshaking.
This I/O model depends on interrupts to receive data at high speed. Once reception has be set up, control will be
returned to the application immediately and the application will need to poll the I/O model for reception completion.
Reception can be suspended and resumed by disabling and enabling interrupts. Turning off interrupts might be required
when going off-line, or for ensuring that other time-critical application execution is not disturbed by background
interrupts. Additionally, SCI reception can also be aborted. Note that sustained reception at 115,200bps can starve the
application processor. Care must be given to allow the PL Smart Transceiver to process received bytes in a timely
manner and update the watchdog timer.
However, data transmission is NOT handled by interrupts; control will be returned to the application only after the last
byte has been placed in the transmission shift register. It is important to note that if previously set up, reception
interrupts will work even while transmission is taking place. This provides a full duplex interface.
DATA
ONE FRAME
87654321
SCI
INPUT
START START
STOP
SCI Output
SCI Input
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO11
Figure 3.35 SCI Input/Output
SPI Input/Output
Pins IO8, IO9 and IO10 can be configured as a serial peripheral interface (SPI) port. The directions of the pins vary with
the configuration. In master mode, pin IO8 is the clock (driven by the PL Smart Transceiver), IO9 is serial data input
(Master In Slave Out or MISO) and IO10 is serial data output (Master Out Slave In or MOSI). In slave mode, pin IO8 is
the clock input, IO9 is serial data output (MISO) and IO10 is serial data input (MOSI). If the Neurowire keyword is
used, the pins assume a Neurowire compatible direction in which IO9 is always output and IO10 is always input. Serial
data is clocked out on the output pin at the same time as it is clocked in on the input pin. In SPI master mode, no other
masters are allowed on the bus. IO7 can be used as a select pin in slave mode, allowing the PL Smart Transceiver to