Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 75
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
Optional Pull-Up Resistors
IO11
t
dw
DATA A
START OF
io_in()
END OF
io_in()
DATA B
TIMEOUT
TIME
t
ibd
t
fin
t
tow
t
tret
t
ret
Symbol Description Min Typ Max
t
fin
Function call to start of second data edge — 75.6 µs —
t
dw
Input data width (at 10MHz) 200 ns 100 µs 880 ms
t
ibd
Inter-bit delay 150 µs — 900 µs
t
tow
Timeout pulse width — 39 µs —
t
tret
Timeout to function return — 18.0 µs —
t
ret
Last data bit to function return — 74.4 µs —
Figure 3.34 Wiegand Input Object
SCI (UART) Input/Output
Pins IO8 and IO10 can be configured as asynchronous SCI (serial communications interface) input and output lines,
respectively. The SCI object model supports the following bit rates for half-duplex transfers when operating at 10MHz:
300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, and 115200 bits per second. The effective transmitted data rate
for half-duplex transfers corresponds to the bit rate at all speeds. There are no inter-byte idle periods and the bit rate of
the input and output can not be independently specified.
For full-duplex transfers, when data is being received and transmitted at the same time, the effective bit rate will be 60%
at 57600 bits per second, and 30% at 115200 bits per second. All other bit rates specified above for half-duplex transfers