Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 69
In Neurowire slave mode, pin IO8 is the clock (driven by the external master), IO9 is the serial data output, and IO10 is
the serial data input. Serial data is clocked out on pin IO9 at the same time as data is clocked in from pin IO10. Data is
clocked by the rising edge of the clock signal (default), which can be up to 18kbps at 10MHz. This data rate scales with
PL Smart Transceiver input clock rate. The invert keyword changes the active clock edge to negative. One of the IO0
– IO7 pins can be designated as a timeout pin. A logic 1 level on the timeout pin causes the Neurowire slave I/O
operation to be terminated before the specified number of bits has been transferred. This prevents the PL Smart
Transceiver watchdog timer from resetting the chip in the event that fewer than the requested number of bits are
transferred by the external clock (see Figure 3.30).
DATA OUT
DATA IN
INPUT
CLOCK
TIME
t
ret
START
OF
io_in()
END OF
io_in()
DATA
OUTPUT
CLOCK
AND DATA
SAMPLED
DATA
OUTPUT
t
docki
t
cklodo
t
cklo
t
fin
CLOCK
SAMPLED
Parameter Description Typ
t
fin
Function call to data bit out 41.4 µs
t
ret
Return from function 19.2 µs
t
docki
Data out to input clock and data sampled 4.8 µs
t
cklo
Data sampled to clock low sampled 24.0 µs
t
cklodo
Clock low sampled to data output 25.8 µs
f Clock frequency (max) 18.31 kHz
Figure 3.30 Neurowire Slave Timing
The algorithm for each bit of output/input for the Neurowire slave objects is described below. In this description, the
default active clock edge (positive) is assumed; if the invert keyword is used, all clock levels stated should be
reversed.
1. Set IO9 to the next output bit value.
2. Test pin IO8, the clock input, for a high level. This is the test for the rising edge of the input clock. If the input clock
is still low, sample the timeout event pin and abort if high.
3. When the input clock is high, store the next data input bit as sampled on pin IO10.