Specifications

Chapter 3 – Input/Output Interfaces
68 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
DATA OUT
DATA IN
CLOCK
SELECT
CLOCK
END OF
io_in() OR io_out()
START OF
io_in() OR io_out()
INPUT SAMPLED
t
setup
t
hold
t
high
t
low
t
fin
t
cs_clock
t
clock_cs
t
ret
Parameter Description Typ
t
fin
Function call to CS~ active 69.9 µs
t
ret
Return from function 7.2 µs
t
hold
Active clock edge to sampling of input data
20 kbps bit rate
10 kbps bit rate
1 kbps bit rate
11.4 µs
53.4 µs
960.6 µs
t
high
Period, clock high (active clock edge = 1)
20 kbps bit rate
10 kbps bit rate
1 kbps bit rate
25.8 µs
67.8 µs
975.0 µs
t
low
Period, clock low (active clock edge = 1) 33.0 µs
t
setup
Data output stable to active clock edge 5.4 µs
t
cs clock
Select active to first active clock edge 91.2 µs
t
clock cs
Last clock transition to select inactive 81.6 µs
f
Clock frequency = 1/(t
high
+ t
low
)
20 kbps bit rate
10 kbps bit rate
1 kbps bit rate
17.0 kHz
9.92 kHz
992 Hz
Figure 3.29 Neurowire Master Timing
Neurowire Slave Mode
The Neurowire slave mode I/O object is still provided for legacy support. Echelon recommends using the hardware SPI
instead of the legacy software I/O object (See SPI Input/Output section). The hardware SPI provides much higher
performance with lower software overhead.