Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 67

Figure 3.28 Neurowire Input/Output

Neurowire Master Mode

The Neurowire master mode I/O object is still provided for legacy support. Echelon recommends using the hardware

SPI instead of the legacy software I/O object (See the SPI Input/Output section later in this manual). The hardware SPI

provides much higher performance with lower software overhead.

In Neurowire master mode, pin IO8 is the clock (driven by the PL Smart Transceiver), IO9 is the serial data output, and

IO10 is the serial data input. Serial data is clocked out on pin IO9 at the same time as data is clocked in from pin IO10.

Data is clocked by the rising edge of the clock signal by default. The clockedge keyword changes the active edge of the

clock to negative. In addition, one or more of the IO0 – IO7 pins can be used as a chip select, allowing multiple

Neurowire devices to be connected on a three-wire bus. The clock rate can be specified as 1kbps, 10kbps, or 20kbps at

an input clock rate of 10MHz; these scale proportionally with input clock (see Figure 3.29).

Data In

Data Out

Clock

Timeout

Neurowire SLAVE

Neurowire MASTER

Data In

Data Out

Clock

Select

IO10

IO9

IO8

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

IO10

IO9

IO8

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

IO11