Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 61
DATA OUT
Active clock edge assumed to be positive in the above diagram.
OUTPUT
CLOCK
END OF
io_in()
START OF
io_in()
t
setup
t
fin
t
aet
t
tae
t
ret
Symbol Description Typ @ 10MHz
t
fin
Function call to first data out stable
16-bit shift count
1-bit shift count
185.3 µs
337.6 µs
t
ret
Return from function 10.8 µs
t
setup
Data out stable to active clock edge
15 kbps bit rate
10 kbps bit rate
1 kbps bit rate
10.8 µs
10.8 µs
10.8 µs
t
aet
Active clock edge to next clock transition
15 kbps bit rate
10 kbps bit rate
1 kbps bit rate
10.2 µs
42 µs
939.5 µs
t
tae
Clock transition to next active clock edge
15 kbps bit rate
10 kbps bit rate
1 kbps bit rate
34.8 µs
34.8 µs
34.8 µs
f
Clock frequency = 1/(t
aet
+ t
tae
)
15 kbps bit rate
10 kbps bit rate
1 kbps bit rate
22 kHz
13 kHz
1.02 kHz
Figure 3.23 Bitshift Output Latency Values
I
2
C Input/Output
This I/O object is used to interface the PL Smart Transceiver to any device which adheres to Philips Semiconductor’s
Inter-Integrated Circuit (I
2
C) bus protocol. The PL Smart Transceiver is always the master, with IO8 being the serial
clock (SCL) and IO9 the serial data (SDA). Alternatively, IO0 can be used as the serial clock (SCL) and IO1 as the
serial data (SDA). These I/O lines are operated in the open-drain mode in order to accommodate the special
requirements of the I
2
C protocol. With the exception of two pull-up resistors, no additional external components are
necessary for interfacing the PL Smart Transceiver to an I
2
C device. Up to 255 bytes of data can be transferred at a time.