Specifications

Chapter 3 – Input/Output Interfaces
58 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
MASTER A0
SLAVE
DATA OUT
READ CYCLE
(MASTER WRITE)
WRITE CYCLE
(MASTER READ)
LATCH
MASTER CS~
MASTER R/W~
MASTER
DATA OUT
t
sbcspw
t
sbcspw
t
spah
t
sbas
t
sbrwh
t
sbrws
t
sbrws
t
sbrdh
t
sbrds
t
sbwdz
t
sbwdh
t
sbwdv
Symbol Description Min Typ Max
t
sbrws
R/W~ setup before falling edge of CS~ PL 3120,
PL 3150, and PL 3170 Smart Transceivers 0 ns — —
t
sbrwh
R/W~ hold after rising edge of CS~ 0 ns — —
t
sbcspw
CS~ pulse width Note 1 — —
t
sbas
A0 setup to falling edge of CS~ 10 ns — —
t
sbah
A0 hold after rising edge of CS~ 0 ns — —
t
sbwdv
CS~ to write data valid — — 50 ns
t
sbwdh
Write data hold after rising edge of CS~ (Notes 2, 3) 0 ns 30 ns —
t
sbwdz
CS~ rising edge to Slave B release data bus (Note 2) — — 50 ns
t
sbrds
Read data setup before rising edge of CS~ 25 ns — —
t
sbrdh
Read data hold after rising edge of CS~ 10 ns — —
Figure 3.20 Slave B Mode Timing
Notes:
1. The slave B write cycle (master read) CS~ pulse width is directly related to the slave B write data valid parameter and master read setup parameter.
To calculate the write cycle CS~ duration needed for a special application use:
t
sbcspw
= t
sbwdv
+ master’s read data setup before rising edge of CS~. Refer to the master’s specification data book for the master read setup
parameter. The slave read cycle minimum CS~ pulse width = 50 ns.
2. Refer to the PL 3120/PL 3150 or PL 3170 Smart Transceiver Datasheets for detailed measurement information.
3. The data hold parameter, t
sbwdh
, is measured to the disable levels shown in the PL 3120/PL 3150 or PL 3170 Smart Transceiver Datasheets, rather
than to the traditional data invalid levels.
4. In a slave B write cycle, the timing parameters are the same for a control register (HS) write as for a data write.
5. Special applications: Both the state of CS~ and R/W~ determine a slave B write cycle. If CS~ cannot be used for a data transfer, then toggling the
R/W~ line can be used with no changes to the hardware. In other words, if CS~ is held low during a slave B write cycle, a positive pulse (low to
high to low) on R/W~ can execute a data transfer. The low to high transition on R/W~ causes slave B to drive data with the same timing
parameters as t
sbwdv
(redefined R/W~ to write data valid). Likewise, the falling edge of
R/W~ causes slave B to release the data bus with
the same timing limits as the CS~ rising edge in t
sbwdz
. This scenario is only true for a slave B write cycle and is not applicable to a slave B read
cycle or any slave A data transitions. This application can be helpful if the master has separate read and write signals but no CS~ signal. Caution
must be taken to ensure the bus is free before transfers to avoid bus contention.