Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 57

Slave B Mode

The slave B mode is recommended for interfacing a PL Smart Transceiver acting as the slave to another microprocessor

acting as the master. When configured in slave B mode, the PL Smart Transceiver accepts IO8 as a chip select and IO9

to specify whether the master will read or write, and accepts IO10 as a register select input. When CS~ is asserted and

either IO10 is low or IO10 is high and R/W~ is low, pins IO0 – IO7 form the bidirectional data bus. When IO10 is high,

R/W~ is high, and CS~ is asserted, IO0 is driven as the HS acknowledgment signal to the master.

The PL Smart Transceiver can appear as two registers in the master’s address space; one of the registers being the

read/write data register, and the other being the read-only status register. Therefore, reads by the master to an odd

address access the status register for handshaking acknowledgments and all other reads or writes access the data register

for I/O transfers. The LSB of the control register, which is read through pin IO0, is the HS bit. The master reads the HS

bit after every master read or write. The D0/HS line should be pulled up (inactive) with a 10kΩ resistor to ensure

proper resynch behavior after resets.

When acting as a slave to a different microprocessor, the PL Smart Transceiver slave B mode handles all handshaking

and token passing automatically. However, the master microprocessor must read the HS bit after each transaction and

must also internally track the token passing. This mode is designed for use with a master processor that uses memory-

mapped I/O, as the LSB of the master’s address bus is typically connected to the IO10 pin of the PL Smart Transceiver.

This is illustrated in Figures 3.19 and 3.20.

IO10 = 1

IO10 = 0

R/W~ = 1

IO10 = 1

READ ONLY

STATUS REGISTER

READ/WRITE

DATA REGISTER

D0/HS

IO10

IO9

IO8

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

R/W~

CS~

SLAVE B

HS/D0 – D7

IO11

R/W~ = 1

R/W~ = 0 OR 1

Figure 3.19 Parallel I/O Master/Slave B (PL Smart Transceiver as Memory-Mapped I/O Device)