Specifications

Chapter 3 – Input/Output Interfaces
56 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
CS~
HS
R/W~
DATA OUT
DATA IN
READ CYCLE
(MASTER WRITE)
WRITE CYCLE
(MASTER READ)
t
sahsv
t
sacspw
t
sahsv
t
sacspw
t
sahsh
t
sarws
t
sarws
t
sahsh
t
sarwh
t
sards
t
sardh
t
sawd
t
sawds
t
sawdh
t
sardz
Symbol Description Min Typ Max
t
sarws
R/W~ setup before falling edge of CS~ 25 ns — —
t
sarwh
R/W~ hold after rising edge of CS~ 0 ns — —
t
sacspw
CS~ pulse width 45 ns — —
t
sahsh
HS hold after rising edge of CS~ 0 ns — —
t
sahsv
HS valid after rising edge of CS~ — — 50 ns
t
sawdd
Slave A drive of DATA after rising edge of R/W~ (Notes 1, 2) 0 ns 5 ns —
t
sawds
Write data valid before falling edge of HS (Note 4) 150 ns 2 XIN —
t
sawdh
Write data valid after rising edge of CS~ (Note 4) 150 ns
(Note 3)
2 XIN —
t
sardz
Slave A three-state DATA after falling edge of R/W~ (Note 1) — — 50 ns
t
sards
Read data setup before rising edge of CS~ 25 ns — —
t
sardh
Read data hold after rising edge of CS~ 10 ns — —
Figure 3.18 Slave A Mode Timing
Notes:
1. Refer to the PL 3120/PL 3150 or PL 3170 Smart Transceiver Datasheets for detailed measurement information.
2. For PL Smart Transceiver-to-PL Smart Transceiver operation, bus contention (t
mrdz
, t
sawdd
) is eliminated by firm-
ware, ensuring that a zero state is present when the token is passed between the master and slave. See Parallel I/O
Interface to the Neuron Chip engineering bulletin for further information.
3. If t
sarwh
< 150ns, then t
sawdh
= t
sarwh
.
4. XIN represents the period of the PL Smart Transceiver input clock (100ns at 10MHz).
5. In slave A mode, the HS signal is high a minimum of 4 XIN periods. The typical time HS is high during consecutive
data reads or consecutive data writes is also 4 XIN periods.