Specifications

Chapter 3 – Input/Output Interfaces
50 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
Nibble Input/Output
Groups of four consecutive pins between IO0 – IO7 can be configured as nibble-wide input or output ports, which can
be read or written to using integers in the range 0 to 15. This is useful for driving devices that require BCD data, or other
data four bits at a time. For example, a 4x4 key switch matrix can be scanned by using one nibble to generate an output
(row select — one of four rows), and one nibble to read the input from the columns of the switch matrix. See Figures
3.12, 3.13, and 3.14.
The direction of nibble ports can be changed between input and output dynamically under application control (see the
Neuron C Programmer’s Guide). The LSB of the input data is determined by the object declaration and can be any of
the IO0 – IO4 pins.
Figure 3.12 Nibble I/O
t
ret
t
fin
TIME
INPUT PIN
SAMPLED
END OF
io_in()
START OF
io_in()
INPUT
Symbol Description Typ @ 10MHz
t
fin
Function call to sample
IO0 – IO4 41 µs
t
ret
Return from function
IO0
IO1
IO2
IO3
IO4
18 µs
22.8 µs
27.5 µs
32.3 µs
37 µs
Figure 3.13 Nibble Input Latency Values
High Current Sink Drivers
Optional Pull-Up Resistors
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO11