Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 49
Leveldetect Input
Pins IO0 – IO7 can be individually configured as leveldetect input pins, which latch a negative-going transition of the
input level with a minimal low pulse width of 200ns, with a PL Smart Transceiver clocked at 10MHz. The application
can therefore detect short pulses on the input which might be missed by software polling. This is useful for reading
devices, such as proximity sensors. This is the only direct I/O object which is latched before it is sampled. The latch
is cleared during the when statement sampling and can be set again immediately after, if another transition should occur
(see Figure 3.11).
1ST NEGATIVE
TRANSITION
IS LATCHED
200ns
SYSTEM
CLOCK
(@ 10MHz)
t
ret
t
fin
TIME
INPUT
LATCH
SAMPLED
AND THEN
CLEARED
END OF
io_in()
START OF
io_in()
INPUT
PIN
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
Optional Pull-Up Resistors
IO7
2ND
NEGATIVE
TRANSITION
IS LATCHED
INPUT
LATCH
IO11
Symbol Description Typ @ 10MHz
t
fin
Function call to sample
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
35 µs
39.4 µs
43.9 µs
48.3 µs
52.7 µs
57.2 µs
61.6 µs
66 µs
t
ret
Return from function 32 µs
Figure 3.11 Leveldetect Input Latency Values