Specifications

Chapter 3 – Input/Output Interfaces

46 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo

Overall accuracy is always related to the accuracy of the XIN input of the PL Smart Transceiver. Timing diagrams are

provided for all non-trivial cases to clarify the parameters given.

For more information on the operation of each of the I/O objects, refer to the Neuron C Reference Guide.

Direct I/O Objects

The timing numbers shown in this section are valid for both an explicit I/O call or an implicit I/O call through a when

clause, and are assumed to be for a PL Smart Transceiver running at 10MHz.

Bit Input/Output

Pins IO0 – IO11 can be individually configured as single-bit input or output ports. Inputs can be used to sense TTL-level

compatible logic signals from external logic, contact closures, and the like. Outputs can be used to drive external CMOS

and TTL level compatible logic, switch transistors and very low current relays to actuate higher-current external devices

such as stepper motors and lights. The high (20mA) current sink capability of pins IO0 – IO3 allows these pins to drive

many I/O devices directly (refer to Figure 3.5). Figures 3.6 and 3.7 show the bit input and bit output latency times,

respectively. These are the times from which io_in() or io_out() is called, until a value is returned. The direction

of bit ports can be changed between input and output dynamically under application control.

(io_set_direction())

IO10

IO9

IO8

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

High Current Sink Drivers Optional Pull-Up Re-

sistors

IO10

IO9

IO8

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

IO11

Figure 3.5 Bit I/O

Note: After a reset, the PL Smart Transceiver disables the IO4-IO7 and IO11 pull-up resistors. The pull-up resistors are

not turned on until application initialization. Pull-ups are only enabled when specified in the application configuration

using a Neuron C directive (#pragma enable_io_pullups).