Specifications

PL 3120/PL 3150/ PL 3170 Power Line Smart Transceiver Data Book 41

Table 3.5 Summary of Timer/Counter Output Objects

I/O Object Applicable I/O Pins Output Signal Page

Edgedivide Output IO0, IO1 + (one of IO4 – IO7) Output frequency is the input fre-

quency divided by a user-specified

number

Infrared Pattern

Output

IO0, IO1 Series of timed repeating square

wave output signals

Frequency Output IO0, IO1 Square wave of 0.3 Hz to 2.5MHz

Oneshot Output IO0, IO1 Pulse of duration 0.2 µs to 1.678 s

Pulsecount Output IO0, IO1 0 – 65,535 pulses

Pulsewidth Output IO0, IO1 0 – 100% duty cycle pulse train

Triac Output IO0, IO1 + (one of IO4 – IO7) Delay of output pulse with respect

to input edge

100

Triggered-

Count Output

IO0, IO1 + (one of IO4 – IO7) Output pulse controlled by counting

input edges

102

To maintain and provide consistent behavior for external events and to prevent metastability, all 12 I/O pins of the PL

Smart Transceiver, when configured as inputs, are passed through a hardware synchronization block sampled by the

internal system clock. This is always the input clock divided by two (e.g. 10MHz ÷ 2 = 5MHz). For any signal to be

reliably synchronized with a 10MHz input clock, it must be at least 220ns in duration (see Figure 3.2).

All inputs are software sampled during when statement processing. The latency in sampling is dependent on the I/O

object which is being executed (see I/O timing specification and the Neuron C Programmer’s Guide for more

information). These latency values scale inversely with the input clock. Thus, any event that lasts longer than 220ns will

be synchronized by hardware, but there will be latency in software sampling resulting in a delay detecting the event. If

the state changes at a faster rate than software sampling can occur, then the interim changes will go undetected.

There are three exceptions to the synchronization block. First, the chip select (CS~) input used in the slave B mode of

the parallel I/O object; this input will recognize rising edges asynchronously. Second, the leveldetect input is latched by

a flip-flop with a 200ns clock. The level detect transition event will be latched, but there will be a delay in software

detection. Third, the SCI (UART) and SPI objects are buffered on byte boundaries by the hardware and are transferred

to memory using an interrupt mechanism. The input timer/counter functions are also different, in that events on the

I/O pins will be accurately measured and a value returned to a register, regardless of the state of the application

processor. However, the application processor can be delayed in reading the register. Consult the Neuron C

Programmer’s Guide for detailed programming information.