Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 31
Stack Initialization and BIST 38.6000 ms
SERVICE~ Pin Initialization 0.1000 ms
State Initialization 0.0250 ms
Off-Chip RAM Initialization 0 ms
Random Number Seed Calculation 0 ms
System RAM Setup 2.7000 ms
Communication Port Initialization 0.0000 ms
Checksum Initialization 10.8000 ms
One-Second Timer Initialization 0.6100 ms
Scheduler Initialization 0.7400 ms
Total 53.5757 ms
Table 2.9 PL 3150 Smart Transceiver Reset Sequence Time
Step Number of XIN Cycles Notes
Stack Initialization and BIST 425,000
SERVICE~ Pin Initialization 1000
State Initialization
1300 (for no boot)
70,000 + 25 ms*E (for boot)
1
Off-Chip RAM Initialization
24,000 + 214*R (for test and clear)
24,000 + 152*R
a
(for clear only)
2
3
Random Number Seed Calculation 50,000 max
System RAM Setup 27,000 + 1500*B 4
Communication Port Initialization 0 5
Checksum Initialization
7200 + 175*M (for no boot)
82,000 + 100 ms + 175*M (for boot)
6, 7
One-Second Timer Initialization 6100
Scheduler Initialization
≥ 7400
8
Notes:
1) E is the number of non-zero bytes being written (ranges from 10 to 504).
2) R is the number of off-chip RAM bytes.
3) R
a
is the number of non-system off-chip RAM bytes.
4) B is the number of application and/or network buffers allocated.
5) These tasks run in parallel with other tasks.
6) M is the number of bytes to be checksummed.
7) Only if booting to the configured or unconfigured state; if booting to the applicationless state, use the “no boot” equation.
8) Assumes a trivial initialization task, no reset task, and the configured state.
For example, the timing of each of these steps is shown for a PL 3150 Smart Transceiver application with the following
parameters: 10MHz input clock, crystal oscillator, no boot required, 16K bytes external RAM, test and clear external
RAM, at least 10 application and/or network buffers, and 500 bytes of EEPROM checksummed.