Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 29
After the oscillator has started up, the PL Smart Transceiver counts additional transitions on XIN to allow the
oscillator’s frequency to stabilize. From the time RESET~ is asserted until the end of the oscillator stabilization period,
the I/O pins are in a high-impedance state. The E~ signal goes inactive (high) immediately after reset goes low, and the
address bus becomes high (0xFFFF) to deselect external devices.
The stack initialization and BIST task tests the on-chip RAM, the timer/counter logic, and the counter logic. For the test
to pass, all three processors and the ROM must be functioning. A flag is set to indicate whether the PL Smart
Transceiver passed or failed the BIST. The RAM is cleared to all 0s by the end of this step. The SERVICE~ pin
oscillates between a solid low and a weak high. The memory interface signals reflect execution of these tasks.
If the RAM self-test fails, the device goes offline, the service LED comes on solid, and an error is logged in the device’s
status structure.
Self-test results are available in the first byte of RAM (0xE800) as follows:
Value Description
0 No Failure
1 RAM failure
2 Timer/counter failure
3 Counter failure
4 Configured input clock rate exceeds the chip maximum
The SERVICE~ pin initialization task turns off the SERVICE~ pin (high state).
The state initialization task determines if a PL Smart Transceiver boot is required (PL 3150 Smart Transceiver only),
and performs the boot if it is required. The PL Smart Transceiver decides to perform a boot if it is blank, or if the boot
ID does not match the boot ID in ROM.
The off-chip RAM initialization task checks the memory map to determine if any off-chip RAM is present and then
either tests and clears all of the off-chip RAM or, optionally, clears the application RAM area only. This choice is
controlled by the application program via a Neuron C compiler directive. This task applies only to the PL 3150 Smart
Transceiver.
The random number seed calculation task creates a seed for the random number generator.
The system RAM setup task sets up internal system pointers as well as the linked lists of system buffers.
The checksum initialization task generates or checks the checksums of the nonvolatile writable memories. If the boot
process was executed for the configured or unconfigured states, in the state initialization task, then the checksums are
generated; otherwise, they are checked. This process includes on-chip EEPROM, off-chip EEPROM, flash, and off-chip
nonvolatile RAM. There are two checksums, one for the configuration image and one for the application image. In each
case, the checksum is a negated two’s complement sum of the values in the image.
The one-second timer initialization task initializes the one-second timer. At this point, the network processor is available
to accept incoming packets.
The scheduler initialization task allows the application processor to perform application-related initialization as follows:
• State wait — Wait for the device to leave the applicationless state.
• Pointer initialization — Perform a global pointer initialization.
• Initialization step — Execute initialization task, which is created by the compiler/linker to handle initialization
of static variables and the timer/counters.