Specifications

Chapter 2 – Hardware Resources
28 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
Scheduler Init
One-Second Timer Init
Checksum Init
Comm Port Init
System RAM Setup
Random Number Seed Calc
Off-Chip RAM
State Init
SERVICE~ Pin Init
Stack Init and BIST
Stable Address Reflecting Firmware Execution
Stable Data Reflecting Firmware Execution
Stable R/W~ Reflecting Firmware Execution
RESET~
IO [10:8, 3:0]
SERVICE~
E~
ADDR [15:0]
DATA [7:0]
R/W~
WARNING: NOT TO SCALE
Low
Disabled
IO [11, 7:4]
Pull-Ups
PL 3150 ONLY
Oscillates
*NOTE: On power up, the oscillator will start running before RESET~ is released.
Oscillator Stabilization*
Oscillator Start-Up*
Oscillates at Divide by 2 of CLK1
Specified by Application
Specified by Application
Figure 2.10 RESET Timeline for PL Smart Transcievers
During internal oscillator start up (after power up), the PL Smart Transceiver waits for the oscillator signal amplitude to
grow before using the oscillator waveform as the system clock. This period depends on the type of oscillator used and its
frequency, and begins as soon as power is applied to the oscillator and is independent of the RESET~ pin.