Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 27
Reset Processes and Timing
During the reset period, the I/O pins are in a high-impedance state. The PL 3150 Smart Transceiver address lines A15 –
A0 are forced to 0xFFFF, R/W~ is forced to 0, and E
is forced to 1. The data lines are driven low, so they will not float
and draw excess current. The SERVICE~ pin is high impedance during reset and the internal pull-up is disabled. Reset
overrides the effect of E~ clock on data lines in that, in normal operations the data bus is only driven in a write cycle
during the E
clock low portion of the bus cycle, while reset forces the data bus to be driven. The steps followed in
preparing the PL Smart Transceiver to execute the application code are discussed below. These steps are summarized in
Figure 2.10.
After the RESET~ pin is released, the PL Smart Transceiver performs hardware and firmware initialization before
executing application programs. These tasks are:
• Oscillator start-up
• Oscillator stabilization
• Stack initialization and built-in self-test (BIST)
• SERVICE~ pin initialization
• State initialization
• Off-chip RAM initialization
• Random number seed calculation
• System RAM setup
• Communication port initialization
• Checksum initialization
• One-second timer initialization
• Scheduler initialization