Specifications

Chapter 2 – Hardware Resources
26 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
V
DD5
PL Smart Transceiver
LVI
To Other
Devices
(100 pF Min
1000 pF Max)
Switch
If using external flash, an external pulse-stretching LVI must be
used (Dallas DS1813-5).
C
E
RESET~
RESET~
GND
IN
Figure 2.9 Example Reset Circuit For PL 3150 Smart Transceiver-based Devices
Power Up Sequence
During power up sequences, the RESET~ pin will be held low by the internal LVI until the power supply is stable.
Likewise, when powering down, the PL Smart Transceiver RESET~ pin is driven low when the power supply goes
below the Smart Transceiver’s minimum operating voltage. Refer to the PL 3120/PL 3150 or PL 3170 Smart
Transceiver Datasheets for LVI trip points.
Software Controlled Reset
When the CPU watchdog timer expires, or a software command to reset occurs, the RESET~ pin is pulled low for 256
XIN clock cycles.
Watchdog Timer
The PL Smart Transceivers are protected against malfunctioning software or memory faults by three watchdog timers,
one for each processor that makes up the Neuron core. If application or system software fails to reset these timers
periodically, the entire PL Smart Transceiver is automatically reset. The watchdog period is approximately 840 ms at a
10MHz input clock rate and scales inversely with the input clock rate. The Watchdog Timer circuit is always active and
cannot be disabled.
ICTMode pin
During normal operation of the PL Smart Transceiver the ICTMode pin should be in a logic low state. This pin can be
used during the production test of a PL 3150 Smart Transceiver-based device to tri-state the memory interface lines for
in-circuit testing (ICT). Driving the ICTMode pin high and the RESET~ pin low places all Smart Transceiver outputs in
tri-state mode. Each PL 3150 reference design from Appendix A includes a pull-down resistor on the ICTMode pin so
that this pin can be driven high by an in-circuit tester. Note that ICT can be performed on PL 3120 and PL 3170 Smart
Transceiver I/O pins by driving the RESET~ pin low – without driving the ICTMode pin. For this reason the ICTMode
pin on all PL 3120/PL 3170 reference designs from Appendix A have their ICTmode pin tied directly to ground.