Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 25
RESET~ Pin
The RESET~ pin is both an input and an output. The RESET~ pin includes an internal current source that acts as a pull-
up resistor. The RESET~ pin acts an output when any of the following events occur:
• The Smart Transceiver’s internal low-voltage indicator (LVI) detects a low voltage condition
•
The Smart Transceiver’s software program initiates a reset event
• The Smart Transceiver’s Watchdog Timer times out
In some cases it is desirable to use the input capability of RESET~ pin to allow other devices to reset the Smart
Transceiver. Examples of external devices that may be used for this purpose include push button switches,
microcontrollers, and external low-voltage detectors.
WARNING: If the proper external reset circuitry is not used, the PL Smart Transceiver can go “applicationless” or
unconfigured. The applicationless or unconfigured state occurs when the checksum error verification routine detects
corruption in memory which could have falsely been detected due to an improper reset sequence.
The following guidelines must be followed in order for the transceiver’s reset functions to operate reliably:
• Any device connected to the RESET~ pin must have an open-drain (or equivalent) output. If an external device
were to actively drive the RESET~ pin high, contention between that device and the Smart Transceiver’s
internal circuitry could result in anomalous behavior ranging from “applicationless” errors to device failure.
•
If any external devices are connected to the RESET~ pin of the Smart Transceiver then a capacitor should be
connected between RESET~ and ground in order to provide noise immunity. The value of this capacitor should
be at least 100pF and must not exceed 1000pF. For even greater noise immunity, two capacitors (totaling
≤1000pF) can be used with one connected from the RESET~ pin to ground and the other from RESET~ to
V
DD5
. These capacitors should be located within 15mm of the Smart Transceiver’s RESET~ pin.
•
During board level in-circuit testing (ICT) the RESET~ pin should be hard wired to ground via a “pogo pin”.
The PL Smart Transceiver is sensitive to disruptions in on the RESET~ pin during the time it is performing its
initial (one time) boot initialization sequence. For in-circuit test purposes a single test point with a trace of
≤2cm to the RESET~ pin is recommended.
• When using an external oscillator to drive the XIN pin of the PL Smart Transceiver, a power-on-pulse-
stretching LVI with a delay ≥10ms is recommended in order to ensure that the external oscillator has stabilized
before the PL Smart Transceiver is released from reset.
• A PL 3150 Smart Transceiver-based device must use an external pulse stretching LVI. This device must not
just stretch reset events caused by low-voltage conditions but other reset events must also be stretched to a
minimum of 10ms. The thresholds for this external LVI must be a minimum of 4.5V and maximum of 4.75V.
Echelon recommends the use of the DS1813-5 LVI from Maxim Integrated Products (www.maxim-ic.com
).
Figure 2.9 shows a typical external reset circuit for a PL 3150 Smart Transceiver.
• A PL 3120 or PL 3170 Smart Transceiver-based device with no external devices attached to the RESET~ pin
does not require an external LVI or any additional capacitance on the RESET~ line.
!