Specifications

Chapter 2 – Hardware Resources
22 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
XIN
XOUT
C
optional
C
optional
PL Smart
Transceiver
Figure 2.8 PL 3120, PL 3150, PL 3170 Smart Transceiver crystal clock connections
The PL Smart Transceiver requires a clock frequency accuracy of ±200ppm over the full range of component tolerances
and operating conditions. Variation within the PL Smart Transceiver IC uses a portion of the overall ±200ppm budget.
The remaining portion of the error budget allocated for total crystal uncertainty is ±85ppm (assuming that the selected
crystal has a load capacitance specification which matches the circuit loading as described above). Total crystal
uncertainty is the combination of the crystal’s initial frequency tolerance plus its temperature and aging tolerances. Note
that a typical crystal aging specification is 5ppm/yr but, since the aging effect tends to follow a logarithmic curve, aging
over a 10 year span is commonly in the range of 10 to 15ppm (contact individual crystal vendors for detailed
specifications regarding their particular products).
If the load capacitance specification of the crystal is not matched to the circuit design then the nominal frequency will
not match the design center and the error budget for the crystal will be reduced. For example, using a 20pF crystal in a
circuit designed to provide 18pF of loading results in about a 40ppm upward shift in the nominal frequency of
oscillation. Thus a 2pF mismatch consumes nearly half of one side of the error budget. The resulting error budget for the
crystal in this particular example would be +45/-125ppm. This example points out the importance of directly copying
the selected reference layout so that differences in trace capacitance do not pull the nominal frequency away from the
design center.
If a 10.0000MHz clock signal is already available elsewhere on a C-band circuit board (6.5536MHz for an A-band
board) then it can be used as a clock source for the PL Smart Transceiver as long as the clock signal meets several
requirements. First the clock must have an accuracy of ±200ppm over all operating conditions. Its duty cycle symmetry
must be no worse than 60/40% when connected to a 33pF load and measured using a 0.9V threshold. In addition the
voltage swing of the clock signal must be within the GND and V
DD5
supply rails of the PL Smart Transceiver. To use
this clock option, the appropriate clock signal should be connected to the XIN pin of the PL Smart Transceiver and the
XOUT pin of the PL Smart Transceiver should be left open. Note also that appropriate high frequency clock distribution
techniques must be used to ensure that a clean clock signal is present at the XIN pin of the PL Smart Transceiver.
The accuracy of any clock oscillator should be checked during the design verification phase of every PL Smart
Transceiver based product. This measurement must be made without adding any capacitance to either the XIN or XOUT
pins of the PL Smart Transceiver. Holding a probe near but not touching the clock lines and then connecting this probe
to a spectrum analyzer with an accurate time-base provides one way to make this measurement without affecting the
frequency of oscillation.