Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 21
System Clock Divide
Chain
Timer/Counter 2
Timer/Counter 1
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
MUX
System Clock Divide
Chain
Control
Logic
Control
Logic
Figure 2.7 Timer/Counter Circuits
Clock Input
The PL Smart Transceiver requires a 10.0000MHz clock signal for C-band operation and a 6.5536MHz signal for A-
band operation. This clock can be provided by connecting an appropriate parallel resonant crystal to the XIN and XOUT
pins of the PL Smart Transceiver as shown in Figure 2.8.
The Smart Transceiver IC includes on-chip crystal load capacitors. If a crystal is chosen with a load capacitance rating
that matches the capacitance provided by the combination of the PL Smart Transceiver IC and the XIN and XOUT
circuit traces, then off-chip load capacitors are not needed. If the developer prefers to use a crystal with a different load
capacitance rating, then each reference layout for the PL smart Transceiver includes provision for optional off-chip
capacitors to tune the design to match different crystals (see Appendix A for a list of reference designs). The schematic
for each reference design includes a table listing crystal and load capacitance options. These tables cover crystal load
capacitance values ranging from 15 to 20pF.
Crystals with load capacitance ratings greater than 20pF should not be used with PL Smart Transceiver chips. Even
though the optional off-chip capacitors would allow centering the frequency of oscillation, using more than 20pF of load
capacitance could prevent the oscillator from starting under worst-case conditions. To further ensure proper oscillator
startup, the ESR specification for the crystal should be ≤60Ω for C-band operation and ≤100Ω for A-band use.