Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 19
Static RAM
The PL Smart Transceivers contain 2048 bytes of static RAM.
The RAM is used to store the following:
• Stack segment, application, and system data
• Network buffers and application buffers
The RAM state is retained as long as power is applied to the device. After reset, releasing the PL Smart Transceiver
initialization sequence will clear the RAM (see the section Reset Processes and Timing for more information).
Pre-programmed ROM
The PL 3120 and PL 3170 Smart Transceivers contain 24,576 bytes of pre-programmed ROM. This memory contains
the Neuron firmware, including the LonTalk protocol stack, real time task scheduler, and system function libraries. The
Neuron firmware for the PL 3150 Smart Transceiver is stored in external memory. The Neuron firmware is supplied
with the NodeBuilder and Mini EVK tools.
PL 3150 Smart Transceiver External Memory Interface
The external memory interface of the PL 3150 Smart Transceiver (the PL 3120 and PL 3170 Smart Transceivers have
no external memory interface) supports up to 42K Bytes of external memory for additional user program and data. The
total address space is 64K Bytes. However, the upper 6k of address space is reserved for internal RAM, EEPROM, and
memory-mapped I/O (see Figures 2.5 and 2.6), leaving 58K Bytes of external address space. Of this space, 16K Bytes is
used by the Neuron firmware. The external memory space can be populated with RAM, ROM, PROM, EPROM,
EEPROM, or flash memory in increments of 256 bytes. The memory map for the PL 3150 Smart Transceiver is shown
in Figure 2.5. The bus has 8 bidirectional data lines and 16 address lines driven by the processor. Two interface lines
(R/W~ and E~) are used for external memory access. Refer to the PL 3150 Smart Transceiver Datasheet for the required
access times for the external memory used. The input clock rates supported by the PL 3150 Smart Transceiver are
10MHz and 6.5536MHz. The Enable Clock (E~) runs at the system clock rate, which is one-half the input clock rate. All
memory, both internal and external, can be accessed by any of the three processors at the appropriate phase of the
instruction cycle. Because the instruction cycles of the three processors are offset by one-third of a cycle with respect to
each other, the memory bus is used by only one processor at a time.
The Neuron 3150 Chip External Memory Interface engineering bulletin provides guidelines for interfacing the PL 3150
Smart Transceiver to different types of memory. A minimum hardware configuration would use one external ROM
(PROM or EPROM), containing both the Neuron firmware and user application code. This configuration would not
allow the system engineer to change the application code over the network after installation. The network image
(network address and connection information) however, could be altered because this information resides in internal EE-
PROM. If application downloads over the network are a requirement for maintenance or upgrade and the application
code will not fit into the internal EEPROM, then external EEPROM or flash will be necessary. Refer to the Neuron C
Programmer’s Guide for guidelines to reduce code size.
The pins used to interface with external memory are listed in Table 2.7. The E~ clock signal is used to generate read (or
write) signals to external memory. The A15 (address line 15) or a programmable array logic (PAL) decoded signal gated
with R/W~ can be used to generate read signals to external memory.