Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 241
The simplest method of verifying the test system background noise is to connect one PLCA-22 Power Line
Communications Analyzer, Echelon Model 58022, to the UUT port of the test system. The PLCA-22 can be used to
monitor the noise level via its signal strength bar graph LED. The signal strength meter displays the mains signal level
after being filtered by the transceiver’s internal digital signal processing. Thus the meter displays only the noise that will
affect the PL Smart Transceiver. The background noise should read no higher than –78dB on the PLCA-22 bar-graph
meter. That is, at most, only the –78dB LED on the signal strength meter should be illuminated. If additional LEDs are
illuminated then the isolator should be tested as described in Chapter 7.
Verification of Query ID Message Amplitude
The amplitude of the attenuated Query ID message should be about 2mVp-p and as described in the Verification of
Background Noise section, however, there will be low frequency noise present on the mains that will be much larger in
amplitude. The consequence of this fact is that it is not practical to make a direct measurement of the attenuated message
using a wide band instrument such as an oscilloscope. It will be very difficult to trigger on the packet given the noise
present. The solution, once again, is to use a frequency-selective instrument.
The PLCA-22 can be used to verify the attenuation of the Query ID message using the unit's signal strength meter. The
UUT must be disconnected from the test system so that only the Query ID message is observed and not the response to
the Query ID message from the UUT. Simply run the production test with the UUT disconnected and monitor the
signal strength LEDs on the PLCA-22. The LEDs up to and including the –72dB LED should illuminate when the Query
ID is transmitted. If more LEDs illuminate (for example, if the –66dB LED illuminates) this indicates that the
attenuation circuit is not operating properly. The key elements to verify are the 4.7 ohm resistor (R2) and the 15k ohm
resistor (R4).
Manufacturing Handling Guidelines
The following section provides manufacturing guidelines regarding both soldering and handling of the PL Smart
Transceivers.
Board Soldering Considerations
All PL Smart Transceiver chips have an IPC/JEDEC Standard J-STD-020C Level 3 Classification. This means that the
parts have a 168-hour floor life once the parts have been removed from the moisture barrier bag (at ≤30ºC and ≤60%
R.H.). To prevent pop-corning during reflow, parts removed from the moisture barrier protection must be reflow
soldered within 168 hours. If they are not, then they must be drybaked. If drybaking is required, the parts should be
baked for 24 hours at 125ºC, or as required per IPC/JEDEC J-STD-033A. The tubes and reels that the PL 3120 and PL
3170 Smart Transceivers are shipped in will not withstand the drybake. The trays that the PL 3150 Smart Transceiver is
shipped in will withstand a drybake of up to 125ºC.
The PL 3120, PL 3150, and PL 3170 Smart Transceiver ICs comply with the European Union Restriction of Hazardous
Substances (RoHS). The maximum peak temperature for PL Smart Transceivers is 260ºC. Consult the solder
manufacturer’s datasheet for recommendations on optimum reflow profile. The actual reflow profile chosen should
consider the peak temperature limitation noted above.
The parts should, if possible, be handled only with properly calibrated mechanical pick and place equipment. Handling
the parts manually increases the risk that the leads will become bent. Bent leads can result in open or short circuit
connections during the board-level assembly process.