Specifications

Appendix D – Manufacturing Test and Handling Guidelines

236 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo

Production Test Guidelines

This appendix describes recommended production test procedures that can be used to verify the communication

functionality of each PL Smart Transceiver-based device. The production test procedure described below is applicable

for PL Smart Transceiver-based devices operating in either the A or C bands.

Physical Layer Production Test

Production Test Strategy

The production test strategy described in this document is not intended as a design verification test. It is assumed that

compliance with the device checklist of Appendix B and communication performance verification in accordance with

Chapter 7 have been fully verified for the product design. Rather, the production test is designed to:

• Identify devices with manufacturing defects in components surrounding the PL Smart Transceivers.

• Identify component substitutions, made over the course of high volume manufacturing that inadvertently impair

power line communication performance by a significant amount. Such detection is not meant to replace re-

qualification of the product design after component substitution, which should be considered a mandatory

process.

In-Circuit Test (ICT)

The basis for the physical layer performance verification test is the assumption of 100% ICT of the printed circuit board

(PCB) for the Unit Under Test (UUT) prior to production functional test. All passive components are to be tested to the

accuracy of the ICT equipment, all transistor diode junctions and betas should be tested, all ICs should have solder

junctions verified via input diode tests, and all PCB traces should be verified for continuity and lack of short circuit

conditions. The PCB reference layouts supplied with the PL Smart Transceiver Development Support Kit (DSK) all

include test points to allow 100% ICT coverage.

Any deviation from 100% ICT coverage will require an extended physical layer test different from the one described in

this document.

The RESET~ pin of the PL Smart Transceiver should be grounded during ICT. This will prevent the chip from

performing an initial boot sequence. An initial boot should only be allowed when the integrity of the V

DD5

supply

and RESET~ signal can be assured for the entire boot sequence. See Chapter 2 for details of the boot process and

timing.