Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 225
Device Checklist
PL Smart Transceiver Development Support Kit (DSK) Reference Design (refer to the DSK and Chapter 2)
Item OK? Description
1
Reference design used:_______________________________________
Use the name of the ZIP archive file containing the reference design document
(for example, PL_3120_DSK_2L1S_TX1_1_R).
2 *
Check that the reference design portion of the circuit is an accurate copy of the reference layout without
any deviations. This check can be performed using a Gerber viewer to overlay the new design with the
reference design. Describe any deviations from the reference layout (note that more than 30 critical
layout features have been carefully designed into each reference layout and thus only very minor well
justified deviations from the reference layout can be accepted):
3
Check that fabrication notes from the DSK layout files are correct and included in the fabrication
documentation for the device (i.e., PCB material, layer thickness, plating and via clearance).
4 *
Verify that “thermal reliefs” have not been added to Q4, Q5, R21, R22 or R23 (note that some PCB
layout tools automatically add thermal reliefs, but proper heat dissipation from these devices requires a
solid copper connection without thermal reliefs).
5 *
Verify that the copper areas that provide thermal coupling between Q4 & Q2B and between Q5 & Q3A
match the reference layout (note that some PCB layout tools automatically modify certain features of
these areas but proper thermal management requires a direct match to the reference layout).
6
Verify that the in-circuit-test (ICT) points of the reference design have been preserved (note that some
PCB layout tools may delete these test points yet ICT is required in order to insure proper component
assembly).
7 *
Check that the layout of the traces to the crystal have not been modified, or if a crystal with a different
pad pattern is chosen verify that the capacitance to ground (approximately proportional to copper area)
of the XIN and XOUT lines still matches that of the reference layout within 25%.
8 *
The crystal has sufficient accuracy and does not exceed the ±85ppm error budget for the sum of the
following:
Frequency or Calibration Tolerance @ +25°C
Frequency Stability over the full operating temperature range
Aging Stability (accounting for the desired life of the product)
9
The specified crystal has an ESR of ≤60Ω for C-band operation and ≤100Ω for A-band operation.
10
The crystal load capacitors (C18, C19 or C26, C27 of the reference design) have been chosen to match
the selected crystal load capacitance rating, as defined in the reference design documentation (schematic
and BOM).
11
The PL Smart Transceiver operating clock frequency has been verified to be sufficiently close to
10.0000MHz for C-band operation (6.5536MHz for A-band) such that after accounting for crystal and
temperature variation, the total frequency deviation from nominal will not exceed ±200ppm.
12
The OOGAS pin has been connected to appropriate V
A
voltage divider and bypass capacitor (R24, R25
and C28). If the device power supply is not an energy storage type, then the OOGAS pin may optionally
be connected directly to VCORE, eliminating R24, R25 and C28. If the selected reference design uses
the 2Ap-p transmit amplifier then the OOGAS pin should be connected directly to the VCORE (an
energy storage power supply is not practical for use with the 2Ap-p amplifier).
13
The component values for the reference design circuitry have been selected for the proper band of
operation (C-band or A-band).
14
The proper part is specified for Q1 of the reference design; either OnSemi BC857BDW1T1G, Philips
BC857BS or Infineon BC857S.