Specifications

PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 205
The overall signal attenuation between the Send PLCA-22 analyzer and Recv PLCA-22 analyzer shown in Table 7.1 is
the sum of the attenuation level of the attenuator circuit and the Attn level of the Send PLCA-22 analyzer plus 6dB
resulting from the use of a 3.5Vp-p transmit level on the Send PLCA-22 analyzer. A properly performing PL Smart
Transceiver-based product will show a low packet error rate (<3%) up to an overall attenuation of 78dB r.e. 7Vpp (72dB
for secondary frequency). Above these attenuations the error rate for the UUT can increase.
If the Recv PLCA analyzer and UUT error rates are not greater than 5% with 90dB of overall attenuation, then there is a
problem with the test setup. Check that everything is setup as shown in Figure 7.9. Note that it is common for the UUT
to work to approximately 6dB more overall attenuation than the Recv PLCA-22 analyzer due to enhancements in the PL
Smart Transceivers.
If the results of this test are worse than expected, it is helpful to know if the problem affects only the performance of the
UUT or if adjacent receivers are also impaired by the presence of UUT. If the receive performance of the Recv PLCA-
22 analyzer was worse than expected, disconnect the UUT and recheck the PLCA-22 analyzer error rate versus
attenuation. If it is determined that the presence of the UUT impairs the performance of the PLCA-22 analyzers then the
UUT might be injecting noise back onto the power line. Note that the same symptoms would also be observed if no
corrections were made to a UUT which previously failed the Excessive Loading Verification test.
If it is determined through a comparison of the UUT's expected and observed error rates that the UUT cannot reliably
receive packets with an overall attenuation of at least 78dB r.e. 7Vp-p, then check the following:
If the UUT includes a switching power supply, ensure that the power supply noise masks of Chapter 5 have
been met.
Compare the values of the coupling circuit components with those recommended in Chapter 4. It is possible
that the wrong value component was inserted and partial, though compromised, receive performance was still
possible.
Examine the PCB to check for solder bridges, broken traces or miss-loaded components.
Re-verify the Unintentional Output Noise Verification test earlier in this chapter.
Re-verify the receive mode impedance of the UUT by repeating the Excessive Loading Verification Test earlier
in this chapter.
Refer to the node checklist in Appendix B for more information about verifying the design of the UUT.
Notes:
The calculation of packet error rate used in the above verification procedure avoids inaccuracies which would result from the
use of CRC error count to compute packet error rate. The material in this note is provided to explain how an accurate
measure of packet error rate is determined.
Packet error rate actually includes both packets received with an incorrect CRC plus any packets which were so weak or
corrupted they were not detected at all. These “missed packets” are, by definition, not included in the CRC error count of a
node. For a physical layer packet error rate of 10%, the percentage of missed packets is generally negligible. Under
conditions where the packet error rate is greater than 10%, a significant portion of the error rate might be due to missed
packets.
The “Packets received by node” field in NodeUtil software yields the actual number of packets correctly received by the
node. Subtracting this number from the total number of packets sent gives the exact packet error count, including missed
packets.
In addition to the number of test packets selected on the PLCA-22 analyzers, the total number of packets sent on the power
line actually includes several control packets sent between the PLCA-22 analyzers. These control packets are used by the
PLCA-22 analyzers to synchronize their settings before the test, and to exchange data related to the test immediately after
the test. Additionally, querying the status of the UUT causes a few packets to be logged. The total overhead is generally 11
packets.
Given the above, a more accurate formula for calculating the physical layer packet error rate with 1000 test packets is then:
PER% = (1011 - # “Packets received by node”) x 100 / 1011
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