Specifications

Chapter 2 – Hardware Resources
10 PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Boo
k
Overview
The PL 3120 Smart Transceiver is a complete SoC (system-on-a-chip) for designs that require up to 4KB of memory.
The PL 3170 Smart Transceiver includes self-contained application program memory, Interoperable Self-Installation
(ISI) library and engine, RTOS, and an application library pre-programmed in ROM. The PL 3150 Smart Transceiver
supports external memory for more complex applications. The major hardware blocks of the processors are the same,
except where noted; see Table 2.1 and Figure 2.1.
Table 2.1 Comparison of PL Smart Transceivers
Characteristic
PL 3150 Smart
Transceiver
PL 3120 Smart
Transceiver
PL 3170 Smart
Transceiver
RAM Bytes 2,048 2,048 2,048
ROM Bytes — 24,576 24,576
ROM Version N/A V 14 V 17
EEPROM Bytes 512 4,096 4,096
General purpose I/O pins 12 12 12
16-Bit Timer/Counters 2 2 2
External Memory Interface Yes No No
Package 64 pin LQFP 38 pin TSSOP 38 pin TSSOP
Media
Access
Control,
Network, &
Application
Processor
2 KB RAM
4 KB EEPROM
(0.5 KB EEPROM
for PL 3150)
24 KB ROM
(PL 3120 only)
Internal
Data
Bus
(0:7)
Internal
Address
Bus
(0:15)
I/O
Block
2 Timer/
Counters
Oscillator,
Clock, and
Control
Neuron Core
PL 3120/PL 3150/PL 3170 Smart Transceiver IC
Transmitter
Receiver
Power Line Transceiver
XIN
XOUT
SERVICE~
RESET~
External Address/Data
Bus (PL 3150 Smart
Transceiver Only)
IO11
IO0
RXC
INTOUT
INTIN
RXIN
TXSENSE
TXBIAS
VCORE
TXDAC
External
Circuitry
Coupling
Circuit
Power
Mains
Figure 2.1 PL Smart Transceiver Block Diagram
Neuron Processor Architecture
The Neuron core is composed of three processors. These processors are assigned to the following functions by the
Neuron firmware.
Processor 1 is the MAC layer processor that handles layers 1 and 2 of the 7-layer LonTalk
®
protocol stack. This
includes driving the communications subsystem hardware and executing the media access control algorithm. Processor 1
communicates with Processor 2 using network buffers located in shared RAM memory.